LG Semicon

GM71C(S)4400C/CL

8

and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if

modify-write and the data output will contain data read from the selected cell; if neither of the

above sets of conditions is satisfied, the condition of the data out (at access time) is

indeterminate.

These parameters are referenced to CAS leading edge in early write cycles and to WE leading

edge in delayed write or a read modify write cycle.

An initial pause of 100us is required after power up followed by a minimum of eight

initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal

refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required.

In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying

data to the device.

Test mode operation specified in this data sheet is 2-bit test function controlled by control

address bits - - - CA0. This test mode operation can be performed by WE-and-CAS-before-RAS

(WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read

cycles or by WCBR refresh cycles. When the state of

two test bits accord each other, the

condition of the output data is low level. In order to end this test mode operation, perform a RAS

only refresh cycle or a CAS-before-RAS refresh cycle.

the specified value. These parameters should be specified in test mode cycles by adding the

above value to the specified value in this data sheet.

10.

11.

12.

13.

14.

15.

16.

17.