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TMS320VC5402AZGU16 Datasheet(PDF) 5 Page - Texas Instruments |
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TMS320VC5402AZGU16 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 98 page  www.ti.com TMS320VC5402A Fixed-Point Digital Signal Processor SPRS015E – SEPTEMBER 2001 – REVISED JANUARY 2005 List of Figures 2-1 144-Ball GGU MicroStar BGA™ (Bottom View) .............................................................................. 10 2-2 144-Pin PGE Low-Profile Quad Flatpack (Top View) ........................................................................ 12 3-1 TMS320VC5402A Functional Block Diagram ................................................................................. 17 3-2 Program and Data Memory Map ................................................................................................ 20 3-3 Extended Program Memory Map ............................................................................................... 21 3-4 Processor Mode Status Register (PMST) ..................................................................................... 21 3-5 Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] .................................................................................................................... 23 3-6 Software Wait-State Control Register (SWCR) [MMR Address 002Bh] ................................................... 24 3-7 Bank-Switching Control Register (BSCR) [MMR Address 0029h] .......................................................... 25 3-8 Host-Port Interface — Nonmultiplexed Mode ................................................................................. 28 3-9 HPI Memory Map ................................................................................................................. 29 3-10 Pin Control Register (PCR) ...................................................................................................... 30 3-11 Multichannel Control Register 1x (MCR1x) .................................................................................... 31 3-12 Multichannel Control Register 2x (MCR2x) .................................................................................... 31 3-13 Receive Channel Enable Registers Bit Layout for Partitions A to H ....................................................... 31 3-14 Transmit Channel Enable Registers Bit Layout for Partitions A to H ....................................................... 32 3-15 Nonconsecutive Memory Read and I/O Read Bus Sequence .............................................................. 35 3-16 Consecutive Memory Read Bus Sequence (n = 3 reads) ................................................................... 36 3-17 Memory Write and I/O Write Bus Sequence ................................................................................... 37 3-18 Transfer Mode Control Register (DMMCRn) .................................................................................. 39 3-19 DMA Channel Enable Control Register (DMCECTL) ......................................................................... 40 3-20 On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0) .......................................... 41 3-21 On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0) ...................................... 42 3-22 DMPREC Register ................................................................................................................ 43 3-23 General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] ................................................ 46 3-24 General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] ................................................. 46 3-25 IFR and IMR ....................................................................................................................... 52 5-1 Tester Pin Electronics ............................................................................................................ 56 5-2 Internal Divide-By-Two Clock Option With External Crystal ................................................................. 58 5-3 External Divide-By-Two Clock Timing .......................................................................................... 60 5-4 Multiply-By-One Clock Timing ................................................................................................... 61 5-5 Nonconsecutive Mode Memory Reads ......................................................................................... 63 5-6 Consecutive Mode Memory Reads ............................................................................................. 64 5-7 Memory Write (MSTRB = 0) ..................................................................................................... 66 5-8 Parallel I/O Port Read (IOSTRB = 0) ........................................................................................... 68 5-9 Parallel I/O Port Write (IOSTRB = 0) ........................................................................................... 69 5-10 Memory Read With Externally Generated Wait States ....................................................................... 70 5-11 Memory Write With Externally Generated Wait States ....................................................................... 71 5-12 I/O Read With Externally Generated Wait States ............................................................................. 71 List of Figures 5 |
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