RTR-7
Status Register (Read Only)
The 16-bit read-only Status Register provides the RTR system status. Read the Status Register by applying a logic
0 to CTRL, CS, and OE, and a logic 1 to RD/WR. The 16-bit contents of the Status Register are read from data
I/O pins DATA(15:0).
Bit
Number
Initial
Condition
Description
Bit 0
[0]
MCSA0. The LSB of the mode code or subaddress as indicated by the logic state of bit 5.
Bit 1
[0]
MCSA1. Mode code or subaddress as indicated by the logic state of bit 5.
Bit 2
[0]
MCSA2. Mode code or subaddress as indicated by the logic state of bit 5.
Bit 3
[0]
MCSA3. Mode code or subaddress as indicated by the logic state of bit 5.
Bit 4
[0]
MCSA4. Mode code or subaddress as indicated by the logic state of bit 5.
Bit 5
[0]
MC/SA. A logic 1 indicates that bits 4 through 0 are the subaddress of the transmit or
receive command. A logic 0 indicates that bits 4 through 0 are a mode code, and that the
last command was a mode command.
Bit 6
[1]
Channel A/B. A logic 1 indicates that the most recent command arrived on Channel A; a
logic 0 indicates that it arrived on Channel B.
Bit 7
[1]
Channel B Enabled. A logic 1 indicates that Channel B is available for both
Bit 8
[1]
Channel A Enabled. A logic 1 indicates that Channel A is available for both reception
and transmission.
Bit 9
[1]
Terminal Flag Enabled. A logic 1 indicates that the Bus Controller has not Bus Control-
ler, via the above mode code, is overriding the host system’s ability to set the Terminal
Flag bit of the status word.
Bit 10
[1]
Busy. A logic 1 indicates the Busy bit is set. This bit is reset when the System Busy bit in
the Control Register is reset.
Bit 11
[0]
Self-Test. A logic 1 indicates that the chip is in the internal self-test mode.
Bit 12
[0]
TA Parity Error. A logic 1 indicates the wrong Terminal Address parity; it Error bit being
set to a logic one, and Channels A and B become disabled.
Bit 13
[0]
Message Error. A logic 1 indicates that a message error has occurred since has been
examined. Message error condition must be removed before reading the Status Register
to reset the Message Error bit.
Bit 14
[0]
Valid Message. A logic 1 indicates that a valid message has been received
Bit 15
[0]
Terminal Active. A logic 1 indicates the device is executing a transmit or
[] - Values in parentheses indicate the initialized values of these bits.
STATUS REGISTER (READ ONLY):
TERM
ACTV
VAL
MESS
MESS
ERR
TAPA
ERR
SELF
TEST
BUSY TFEN CH A
EN
CH B
EN
CHNL
A/B
MC/
SA
MCSA
4
MCSA
3
MCSA
2
MCSA
1
MCSA
0
[0]
[0]
[0]
[0]
[0]
[1]
[1]
[1]
[1]
[1]
[0]
[0]
[0]
[0]
[0]
[0]
MSB
LSB
[] defines reset state
Figure 4b. Status Register
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