8

COMMERCIALTEMPERATURERANGE

IDT72V70210 3.3V TIME SLOT INTERCHANGE

DIGITAL SWITCH 1,024 x 1,024

Reset Value:

Bit

Name

Description

15-10

Unused

Must be zero for normal operation.

9

MBP

When 1, the connection memory block programming feature is ready for the programming of Connection Memory high bits,

(Memory Block Program)

bit 11 to bit 15. When 0, this feature is disabled.

8-5

BPD4-0

These bits carry the value to be loaded into the connection memory block whenever the memory block programming feature

(Block Programming Data)

is activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD3-0 are

loaded into bit 15 and 12 of the connection memory. Bit 11 to bit 0 of the connection memory are set to 0.

4

BPE

A zero to one transition of this bit enables the memory block programming function. The BPE and BPD4-0 bits in the CR

(Begin Block

register have to be defined in the same write operation. Once the BPE bit is set HIGH, the device requires two frames to

Programming Enable)

complete the block programming. After the programming function has finished, the BPE bit returns to zero to indicate the

operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort to ensure proper operation. When

BPE = 1, the other bit in the CR register must not be changed for two frames to ensure proper operation.

3

OSB

When ODE = 0 and OSB = 0, the output drivers of TX0 to TX31 are in high impedance mode. When ODE = 0 and OSB = 1,

(Output Stand By)

the output driver of TX0 to TX31 function normally. When ODE = 1, TX0 to TX31 output drivers function normally.

2

SFE

A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR register changes from

(Start Frame Evaluation)

zero to one, the evaluation procedure stops. To start another fame evaluation cycle, set this bit to zero for at least one frame.

1-0

Unused

Must be zero for normal operation.

15

14

13

12

11

10

9876543210

000000

MBP

BPD3

BPD2

BPD1

BPD0

BPE

OSB

SFE

0

0

TABLE 5 — CONTROL REGISTER (CR) BITS

TABLE 6 — CONNECTION MEMORY BITS

Bit

Name

Description

15

LPBK

When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback operations, set the delay

(Per Channel Loopback)

offset register bits OFn[2:0] to zero for the streams which are in the loopback mode.

14

V/C(Variable/Constant

This bit is used to select between the variable (LOW) and constant delay (HIGH) mode on a per-channel basis.

ThroughputDelay)

13

P C

When 1, the contents of the connection memory are output on the corresponding output channel and stream. Only the lower

(Processor Channel)

byte (bit 7 – bit 0) will be output to the TX output pins. When 0, the contents of the connection memory are the data memory

address of the switched input channel and stream.

12

OE

This bit enables the TX output drivers on a per-channel basis. When 1, the output driver functions normally. When 0, the output

(OutputEnable)

driver is in a high-impedance state.

11-7

SAB4-0 (Source Stream

The binary value is the number of the data stream for the source of the connection.

Address Bits)

6-5

Unused

Must be zero for normal operation.

4-0

CAB4-0 (Source Channel

The binary value is the number of the channel for the source of the connection.

Address Bits)

15

14

13

12

11

10

9876543210

LPBK

V/C

PC

OE

SAB4

SAB3

SAB2

SAB1

SAB0

0

0

CAB4

CAB3

CAB2

CAB1

CAB0