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HX6228TEHT Datasheet(PDF) 1 Page - Honeywell Solid State Electronics Center |
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HX6228TEHT Datasheet(HTML) 1 Page - Honeywell Solid State Electronics Center |
1 / 12 page RADIATION • Fabricated with RICMOS™ IV Silicon on Insulator (SOI) 0.7 µm Process (L eff = 0.55 µm) • Total Dose Hardness through 1x106 rad(SiO 2) • Neutron Hardness through 1x1014 cm-2 • Dynamic and Static Transient Upset Hardness through 1x1011 rad (Si)/s • Dose Rate Survivability through <1x1012 rad(Si)/s • Soft Error Rate of <1x10-10 upsets/bit-day in Geosynchronous Orbit • No Latchup 128K x 8 STATIC RAM—SOI HX6228 OTHER • Read/Write Cycle Times ≤ 16 ns (Typical) ≤ 25 ns (-55 to 125°C) • Typical Operating Power <25 mW/MHz • Asynchronous Operation • CMOS or TTL Compatible I/O • Single 5 V ± 10% Power Supply • Packaging Options - 32-Lead Flat Pack (0.820 in. x 0.600 in.) - 40-Lead Flat Pack (0.775 in. x 0.710 in.) Military & Space Products GENERAL DESCRIPTION The 128K x 8 Radiation Hardened Static RAM is a high performance 131,072 word x 8-bit static random access memory with industry-standard functionality. It is fabricated with Honeywell’s radiation hardened technology, and is designed for use in systems operating in radiation environ- ments. The RAM operates over the full military temperature range and requires only a single 5 V ± 10% power supply. The RAM is wire bond programmable for either TTL or CMOS compatible I/O. Power consumption is typically less than 25 mW/MHz in operation, and less than 5 mW in the low power disabled mode. The RAM read operation is fully asynchro- nous, with an associated typical access time of 15 ns at 5V. Honeywell’s enhancedSOI RICMOS™IV (Radiation Insen- sitive CMOS) technology is radiation hardened through the use of advanced and proprietary design, layout and process hardening techniques. The RICMOS™ IV process is an advanced 5-volt, SIMOX CMOS technology with a 150 Å gate oxide and a minimum feature size of 0.7 µm (0.55 µm effective gate length—L eff). Additional features include Honeywell’s proprietary SHARP planarization process, and a lightly doped drain (LDD) structure for improved short channel reliability. A 7 transistor (7T) memory cell is used for superior single event upset hardening, while three layer metal power bussing and the low collection volume SIMOX substrate provide improved dose rate hardening. FEATURES |
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