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MC74HC589ADR2 Datasheet(PDF) 7 Page - ON Semiconductor |
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MC74HC589ADR2 Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 12 page MC74HC589A http://onsemi.com 7 TEST CIRCUIT Figure 9. *Includes all probe and jig capacitance CL* TEST POINT DEVICE UNDER TEST OUTPUT CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. 1 k Ω PIN DESCRIPTIONS DATA INPUTS A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7) Parallel data inputs. Data on these inputs are stored in the data latch on the rising edge of the Latch Clock input. SA (Pin 14) Serial data input. Data on this input is shifted into the shift register on the rising edge of the Shift Clock input if Serial Shift/Parallel Load is high. Data on this input is ignored when Serial Shift/Parallel Load is low. CONTROL INPUTS Serial Shift/Parallel Load (Pin 13) Shift register mode control. When a high level is applied to this pin, the shift register is allowed to serially shift data. When a low level is applied to this pin, the shift register accepts parallel data from the data latch. Shift Clock (Pin 11) Serial shift clock. A low–to–high transition on this input shifts data on the serial data input into the shift register and data in stage H is shifted out QH, being replaced by the data previously stored in stage G. Latch Clock (Pin 12) Data latch clock. A low–to–high transition on this input loads the parallel data on inputs A–H into the data latch. Output Enable (Pin 10) Active–low output enable A high level applied to this pin forces the QH output into the high impedance state. A low level enables the output. This control does not affect the state of the input latch or the shift register. OUTPUT QH (Pin 9) Serial data output. This pin is the output from the last stage of the shift register. This is a 3–state output. |
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