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4 page 
MC74HC589A http://onsemi.com 4 TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V – 55 to 25 _C v 85_C v 125_C Unit tsu Minimum Setup Time, A–H to Latch Clock (Figure 5) 2.0 3.0 4.5 6.0 100 TBD 20 17 125 TBD 25 21 150 TBD 30 26 ns tsu Minimum Setup Time, Serial Data Input SA to Shift Clock (Figure 6) 2.0 3.0 4.5 6.0 100 TBD 20 17 125 TBD 25 21 150 TBD 30 26 ns tsu Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock (Figure 7) 2.0 3.0 4.5 6.0 100 TBD 20 17 125 TBD 25 21 150 TBD 30 26 ns th Minimum Hold Time, Latch Clock to A–H (Figure 5) 2.0 3.0 4.5 6.0 25 TBD 5 5 30 TBD 6 6 40 TBD 8 7 ns th Minimum Hold Time, Shift Clock to Serial Data Input SA (Figure 6) 2.0 3.0 4.5 6.0 5 5 5 5 5 5 5 5 5 5 5 5 ns tw Minimum Pulse Width, Shift Clock (Figure 2) 2.0 3.0 4.5 6.0 75 TBD 15 13 95 TBD 19 16 110 TBD 23 19 ns tw Minimum Pulse Width, Latch Clock (Figure 1) 2.0 3.0 4.5 6.0 80 TBD 16 14 100 TBD 20 17 120 TBD 24 20 ns tw Minimum Pulse Width, Serial Shift/Parallel Load (Figure 4) 2.0 3.0 4.5 6.0 80 TBD 16 14 100 TBD 20 17 120 TBD 24 20 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 1000 TBD 500 400 1000 TBD 500 400 1000 TBD 500 400 ns NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D). |
