HX6228

7

WRITE CYCLE AC TIMING CHARACTERISTICS (1)

Symbol

Parameter

Typical

-55 to 125

Units

(2)

Min

Max

Worst Case (3)

TAVAVW

13

25

ns

TWLWH

Write Enable Write Pulse Width

9

20

ns

TSLWH

Chip Select to End of Write Time

12

20

ns

TDVWH

Data Valid to End of Write Time

9

15

ns

TAVWH

Address Valid to End of Write Time

10

20

ns

TWHDX

Data Hold Time after End of Write Time

0

0

ns

TAVWL

Address Valid Setup to Start of Write Time

0

0

ns

TWHAX

Address Valid Hold after End of Write Time

0

0

ns

TWLQZ

Write Enable to Output Disable Time

5

0

9

ns

TWHQX

Write Disable to Output Enable Time

12

5

ns

TWHWL

Write Recovery Time

4

5

ns

TEHWH

Chip Enable to End of Write Time

11

20

ns

(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and

output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive

load of 5 pF for TWLQZ.

(2) Typical operating conditions: VDD=5.0 V, TA=25

°C, pre-radiation.

(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125

°C, post total dose at 25°C.

(4) TAVAVW = TWLWH + TWHWL.

ADDRESS

HIGH

IMPEDANCE

DATA OUT

NWE

DATA IN

DATA VALID

NCS

CE