128Mb: x4, x8, x16
DDR SDRAM
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
5
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SpecTek reserves the right to change products or specifications
without notice.
© 2001, 2002, 2004 SpecTek
CAPACITANCE (x4, x8)
(25°C < TA < +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Delta Input/Output Capacitance: DQs, DQS, DM
DCIO
--
0.50
pF
24
Delta Input Capacitance: Command and Address
DCI1
--
0.50
pF
29
Delta Input Capacitance: CK, CK#
DCI2
--
0.25
pF
29
Delta Input Capacitance: DQs, DQS, DM
CIO
4.0
5.0
pF
Input Capacitance: Command and Address
CI1
2.0
3.0
pF
Input Capacitance: CK, CK#
CI2
2.0
3.0
pF
Input Capacitance: CKE
CI3
2.0
3.0
pF
IDD SPECIFICATIONS AND CONDITIONS (x4, x8)
(25°C < TA < +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
PARAMETER/CONDITION
SYMBOL
-75
-8
UNITS
NOTES
OPERATING CURRENT: One bank; Active-Precharge;
tRC = tRC (MIN);
tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two clock cycles;
IDD0
105
100
mA
22, 48
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2;
tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control
inputs changing once per clock cycle
IDD1
120
115
mA
22, 48
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode;
tCK = tCK(MIN); CKE=LOW;
IDD2P
10
10
mA
23, 32,
50
IDLE STANDBY CURRENNT: CS# = HIGH; All banks idle;
tCK = tCK
(MIN); CKE = HIGH; Address and other control inputs changing once per
clock cycle. VIN = VREF for DQ, DQS, and DM
IDD2N
50
45
mA
51
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode;
tCK = tCK (MIN); CKE = LOW
IDD3P
18
18
mA
23, 32,
50
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank;
Active-Precharge;
tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.
IDD3N
50
45
mA
22
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
tCK =
tCK (MIN); IOUT = 0mA
IDD4R
120
110
mA
22, 48
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
tCK =
tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
IDD4W
120
110
mA
22
AUTO REFRESH CURRENT
tRC = tRFC (MIN)
IDD5
250
225
mA
22, 50
SELF REFRESH CURRENT (Part number ‘R’ only)
IDD72
2
mA
11
OPERATING CURRENT: Four bank interleaving READs (BL = 4) with
auto precharge,
tRC = tRC (MIN); tCK = tRC (MIN); Address and control
inputs change only during Active, READ, or WRITE commands.
IDD8
330
285
mA
22, 49
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