HD6432351TE datasheet(7/989 Pages) RENESAS

Part #	HD6432351TE

Description	The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

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Manufacturer	RENESAS [Renesas Technology Corp]

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Contents

Section 1

Overview............................................................................................................

1

1.1

Overview............................................................................................................................

1

1.2

Block Diagram ...................................................................................................................

5

1.3

Pin Description...................................................................................................................

6

1.3.1

Pin Arrangement ...................................................................................................

6

1.3.2

Pin Functions in Each Operating Mode................................................................

8

1.3.3

Pin Functions ........................................................................................................

13

Section 2

CPU ..................................................................................................................... 21

2.1

Overview............................................................................................................................

21

2.1.1

Features .................................................................................................................

21

2.1.2

Differences between H8S/2600 CPU and H8S/2000 CPU ..................................

22

2.1.3

Differences from H8/300 CPU .............................................................................

23

2.1.4

Differences from H8/300H CPU ..........................................................................

23

2.2

CPU Operating Modes .......................................................................................................

24

2.3

Address Space....................................................................................................................

29

2.4

Register Configuration .......................................................................................................

30

2.4.1

Overview...............................................................................................................

30

2.4.2

General Registers..................................................................................................

31

2.4.3

Control Registers ..................................................................................................

32

2.4.4

Initial Register Values ..........................................................................................

34

2.5

Data Formats......................................................................................................................

35

2.5.1

General Register Data Formats.............................................................................

35

2.5.2

Memory Data Formats ..........................................................................................

37

2.6

Instruction Set ....................................................................................................................

38

2.6.1

Overview...............................................................................................................

38

2.6.2

Instructions and Addressing Modes......................................................................

39

2.6.3

Table of Instructions Classified by Function........................................................

41

2.6.4

Basic Instruction Formats .....................................................................................

51

2.7

Addressing Modes and Effective Address Calculation......................................................

52

2.7.1

Addressing Mode..................................................................................................

52

2.7.2

Effective Address Calculation ..............................................................................

55

2.8

Processing States................................................................................................................

59

2.8.1

Overview...............................................................................................................

59

2.8.2

Reset State ............................................................................................................

60

2.8.3

Exception-Handling State .....................................................................................

61

2.8.4

Program Execution State ......................................................................................

64

2.8.5

Bus-Released State................................................................................................

64

2.8.6

Power-Down State ................................................................................................

64

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