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EL4511CU-T13 Datasheet(PDF) 2 Page - Intersil Corporation |
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EL4511CU-T13 Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 24 page 2 FN7009.7 July 21, 2005 IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Absolute Maximum Ratings (T A = 25°C) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . (VS to GND) +6V Pin Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V, VS +0.3V VCCA1, VCCA2 & VCCD . . . . . . . . . . . . . . . .Must Be Same Voltage Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications VS = VCCA1 = VCCA2 = VCCD = +5V, TA = 25°C, NTSC input signal on SYNCIN, no output loads, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT GENERAL ISD Digital Supply Current (Note 1) 15 20 mA Standby PDWN = VCCD (Note 2) 4 20 µA ISA2 Rate Acquisition Oscillator Supply Current (Note 1) 3 20 mA Standby PDWN = VCCD 2.5 20 µA ISA1 Analog Processing Supply Current (Note 1) 3 20 mA Standby PDWN = VCCD (Note 2) 3 20 µA COMPOSITE SYNC INPUT AT SYNCIN VSYNC Sync Signal Amplitude AC coupled to SYNCIN pin (Notes 1 & 3) 140 600 mV VSLICE Slicing Level of Sync Signal After sync lock is attained, see description 50 % HORIZONTAL AND VERTICAL INPUT AT HIN, VERTIN HSLICE, VSLICE Slice Level of HIN and VERTIN 1.4 V THINL H Sync Width (Bi-Level) 312.8 % of H time (Tri-Level) Minimum Sync Width 1.4 % of H time FHINH H Sync Frequency 10.75 150 kHz TVINL V Sync Width 27 H lines FVINH V Sync Frequency 23 100 Hz LOGIC OUTPUT SIGNALS, HOUT, VOUT, VBLANK, BACKPORCH, ODD/EVEN, SYNCLOCK O/PLOW Logic Low State 1.6mA, VCCD = 5V GNDD+0.4 V 1.6mA, VCCD = 3.3V GNDD+0.5 O/PHI Logic High State 1.6mA, VCCD = 5V VCCD-0.4 V 1.6mA, VCCD = 3.3V VCCD-0.5 TdHOUT HOUT Timing Relative to Input See timing diagrams 1, 2, 3 & 4 TdSYNCOUT SYNCOUT Timing Relative to Input See timing diagrams 1, 2, 3 & 4 TdBACKPORCH BACKPORCH Timing Relative to Input See timing diagrams 1, 2, 3 & 4 LEVEL OUTPUT DRIVER, LEVEL VLEVEL 2 X Amplitude of VSYNC Refer to description of operation 1.9x 2.15x 2.4x ZLEVEL O/P Resistance of Driver Stage 450 Ω EL4511 |
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