6

_______________________________________________________________________________________

Pin Description

PIN

NAME

FUNCTION

1

Q0

Noninverting Differential Output 0. Typically terminated with 100

Ω to Q0.

2

Q0

Inverting Differential Output 0. Typically terminated with 100

Ω to Q0.

3

Q1

Noninverting Differential Output 1. Typically terminated with 100

Ω to Q1.

4

Q1

Inverting Differential Output 1. Typically terminated with 100

Ω to Q1.

5

Q2

Noninverting Differential Output 2. Typically terminated with 100

Ω to Q2.

6

Q2

Inverting Differential Output 2. Typically terminated with 100

Ω to Q2.

7

Q3

Noninverting Differential Output 3. Typically terminated with 100

Ω to Q3.

8

Q3

Inverting Differential Output 3. Typically terminated with 100

Ω to Q3.

9

Q4

Noninverting Differential Output 4. Typically terminated with 100

Ω to Q4.

10

Q4

Inverting Differential Output 4. Typically terminated with 100

Ω to Q4.

11

GND

Ground

12

CLKSEL

Clock Select Input. Drive low to select the CLK0, CLK0 input. Drive high to select the CLK1,

Ω pulldown to GND.

13

CLK0

Noninverting Differential Clock Input 0. Internal 75k

Ω pulldown to GND.

14

CLK0

Inverting Differential Clock Input 0. Internal 75k

15

Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a

reference for single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to

16

CLK1

Noninverting Differential Input 1. Internal 75k

Ω pulldown to GND.

17

CLK1

Inverting Differential Input 1. Internal 75k

18, 20

the capacitors as close to the device as possible with the smaller value capacitor closest to the

device.

19

EN

Output Enable Input. Outputs are synchronously enabled on the falling edge of the selected

clock input when EN is low. Outputs are synchronously driven to a differential low state on the

falling edge of the selected clock input when EN is high. Internal 60k

Ω pulldown to GND

(Figure 3).

1:5 Clock Driver with Selectable LVPECL

Inputs/Single-Ended Inputs and LVDS Outputs