9

Table 4. HDMP-2689 Transmitter Section Timing Characteristics,

Symbol

Parameters

Units

Min

Typ

Max

1G

Tx

CDS

[1,2]

Clock to data skew time; the data must be stable by T

ps

300

guarantee correct clocking of the data

Tx

H

[2]

Hold time; the time after the clock edge until which the data must remain stable

ps

2000

to guarantee correct clocking of the data

Transmitter latency; the time between the latching edge of the transmit byte clock

ns

80

TCn and the leading edge of the first transmitted serial output bit in buffer mode

bits

85

Transmitter latency; the time between the leading edge of the transmit byte clock

ns

90

TCn and the leading edge of the first transmitted serial output bit in codec mode

bits

95.5

2G

Tx

CDS

[1,2]

Clock to data skew time; the data must be stable by T

ps

300

guarantee correct clocking of the data

Tx

H

[2]

Hold time; the time after the clock edge until which the data must remain stable to

ps

2000

guarantee correct clocking of the data

Transmitter latency; the time between the latching edge of the transmit byte clock

ns

65

TCn and the leading edge of the first transmitted serial output bit in buffer mode

bits

138

Transmitter latency; the time between the leading edge of the transmit byte clock

ns

70

TCn and the leading edge of the first transmitted serial output bit in codec mode

bits

149

Notes:

1. This clock-to-data skew time is equivalent to –300ps setup time.

2. Measurement conditions were V

3. Due to the FIFO which aligns the phase of the internal chip clock with the transmit byte clock (TCn) and the asynchronous nature of the chip reset, the

typical latency varies; a maximum of the typical range is given.

Figure 9. Transmitter Timing Diagram.

9.4 ns

TCn

TDn[9:0]

Tx

H

Tx

CDH

Case A. Tx Half Rate SDR Timing

9.4 ns

TCn

TDn[9:0]

Tx

H

Tx

CDH

Case B. Tx Full Rate DDR Timing

Tx

CDH

Tx

H

Test Conditions: V