9

COMMERCIAL AND INDUSTRIAL

TEMPERATURERANGES

IDT72261LA/72271LA SuperSync FIFO™

16,384 x 9 and 32,768 x 9

Figure 4. Programmable Flag Offset Programming Sequence

Figure 3. Offset Register Location and Default Values

EMPTY OFFSET (LSB) REG.

8

7

0

EMPTY OFFSET (MSB) REG.

00H

85

0

IDT72261LA

 16,384 x 9  BIT

FULL OFFSET (LSB) REG.

8

7

0

FULL OFFSET (MSB) REG.

00H

85

0

DEFAULT VALUE

07FH if

LD is LOW at Master Reset

3FFH if

LD is HIGH at Master Reset

DEFAULT VALUE

07FH if

LD is LOW at Master Reset

3FFH if

LD is HIGH at Master Reset

4671 drw 06

IDT72271LA

 32,768 x 9  BIT

EMPTY OFFSET (LSB) REG.

8

7

0

EMPTY OFFSET (MSB) REG.

00H

86

0

FULL OFFSET (LSB) REG.

8

7

0

FULL OFFSET (MSB) REG.

00H

86

0

DEFAULT VALUE

07FH if

LD is LOW at Master Reset

3FFH if

LD is HIGH at Master Reset

DEFAULT VALUE

07FH if

LD is LOW at Master Reset

3FFH if

LD is HIGH at Master Reset

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

WCLK

RCLK

Selection

X

Parallel write to registers:

Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (MSB)

X

Parallel read from registers:

Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (MSB)

X

X

No Operation

X

Write Memory

X

Read Memory

X

X

No Operation

4671 drw 07

LD

0

0

X

1

1

1

0

WEN

0

1

1

0

X

1

1

REN

1

0

1

X

0

1

1

X

Serial shift into registers:

28 bits for the 72261LA

SEN

1

1

1

X

X

X

0

30 bits for the 72271LA

1 bit for each rising WCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)