7

FN7506.0

February 14, 2005

Description of Operation and Application

Information

Product Description

The EL5624A is fabricated using a high voltage CMOS

process. It exhibits rail to rail input and output capability and

has very low power consumption. When driving a load of

10K and 12pF, this buffer has a -3dB bandwidth of 12MHz

-3dB bandwidth of 35MHz and exhibit 70V/µs slew rate.

Input, Output, and Supply Voltage Range

The EL5624A is specified with a single nominal supply

voltage from 5V to 15V or a split supply with its total range

from 5V to 15V. Correct operation is guaranteed for a supply

range from 4.5V to 16.5V.

The input common-mode voltage range of the EL5624A

extends 500mV beyond the supply rails. The output swings

100mV of the positive and negative supply rails with load

currents of 5mA. Decreasing load currents will extend the

output voltage even closer to each supply rails.

Output Phase Reversal

The EL5624A is immune to phase reversal as long as the

Although the device's output will not change phase, the

input's overvoltage should be avoided. If an input voltage

exceeds supply voltage by more than 0.6V, electrostatic

protection diode placed in the input stage of the device begin

to conduct and overvoltage damage could occur.

FIGURE 19. OPEN LOOP GAIN AND PHASE vs FREQUENCY

FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

100

60

-60

-100

20

-20

1K

100M

10K

100K

1M

10M

FREQUENCY (Hz)

150

-150

50

-50

PHASE

GAIN

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

1

0.9

0.6

0.4

0.3

0.2

0.1

0

0

255075

100

150

AMBIENT TEMPERATURE (°C)

85

0.8

0.5

0.7

125

800mW

θ

125

°C

/W

HT

SS

OP

20

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD - HTSSOP EXPOSED

DIEPAD SOLDERED TO PCB PER JESD51-5

3.5

3

2.5

1.5

1

0.5

0

0

255075

100

150

AMBIENT TEMPERATURE (°C)

2.857W

θ

35

°C

/W

HT

SS

OP

20

125

85

2

EL5624A