6

To facilitate the system designs that use multiple EL5325

chips, a buffered serial output of the shift register (SDO pin)

is available. Data appears on the SDO pin at the 16th falling

SCLK edge after being applied to the SDI pin.

To control the multiple EL5325 chips from a single three-wire

serial port, just connect the ENA pins and the SCLK pins

together, connect the SDO pin to the SDI pin on the next

chip. While the ENA is held low, the 16m-bit data is loaded to

the SDI input of the first chip. The first 16-bit data will go to

the last chip and the last 16-bit data will go to the first chip.

While the ENA is held high, all addressed outputs will be

updated simultaneously.

The Serial Timing Diagram and parameters table show the

timing requirements for three-wire signals.

The serial data has a minimum length of 16 bits, the MSB

(most significant bit) is the first bit in the signal. The bits are

allocated to the following functions (also refer to the Control

Bits Logic Table)

• Bit 15 is always set to a zero

• Bit 14 controls the source of the clock, see the next

section for details

• Bits 13 through 10 select the channel to be written to,

these are binary coded with channel A = 0, and channel

H= 7

• The 10-bit data is on bits 9 through 0. Some examples of

data words are shown in the table of Serial Programming

Examples

Serial Timing Diagram

TABLE 1. CONTROL BITS LOGIC TABLE

BIT

NAME

DESCRIPTION

B15

Test

Always 0

B14

Oscillator

0 = Internal, 1 = External

B13

A3

Channel Address

B12

A2

Channel Address

B11

A1

Channel Address

B10

A0

Channel Address

B9

D9

Data

B8

D8

Data

B7

D7

Data

B6

D6

Data

B5

D5

Data

B4

D4

Data

B3

D3

Data

B2

D2

Data

B1

D1

Data

B0

D0

Data

B15

B14

B13

B12-B2

B1

B0

ENA

SCLK

SDI

MSB

LSB

t

Load MSB first, LSB last

EL5325