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A6832SEP Datasheet(PDF) 4 Page - Allegro MicroSystems |
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A6832SEP Datasheet(HTML) 4 Page - Allegro MicroSystems |
4 / 7 page 4 Worcester, Massachusetts 01615-0036 (508) 853-5000 115 Northeast Cutoff, Box 15036 www.allegromicro.com A6832 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Timing Requirements and Specifications (Logic Levels are VDD and Ground) CLOC K SER IAL DAT A IN ST R OB E OUT P UT E NAB LE OUT N 50% SER IAL DAT A OUT DAT A DAT A 10% 90% 50% 50% 50% C A B D E HIG H = ALL OUT P UT S E NAB LE D p(S T H-QL) t p(C H-S QX) t DAT A p(S T H-QH) t OUT P UT E NAB LE OUT N DAT A 10% 50% dis (B Q) t en(B Q) t LOW = ALL OUT P UT S BLANKE D (DIS ABLE D) r t f t 50% 90% NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be attainable; operation at high temperatures will reduce the specified maximum clock frequency. Serial Data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be low during serial data entry. When the OUTPUT ENABLE input is low, the output sink drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input high, the outputs are controlled by the state of their respective latches. Key Description Symbol Time (ns) A Data Active Time Before Clock Pulse (Data Set-Up Time) tsu(D) 25 B Data Active Time After Clock Pulse (Data Hold Time) th(D) 25 C Clock Pulse Width tw(CH) 50 D Time Between Clock Activation and Strobe tsu(C) 100 E Strobe Pulse Width tw(STH) 50 |
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