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TZA3005 Datasheet(PDF) 8 Page - NXP Semiconductors |
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TZA3005 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 24 page  1997 Aug 05 8 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005 The REFSEL0 and REFSEL1 inputs, in combination with the MODE input, select the ratio between the output clock frequency and the reference input frequency (see Table 3). This ratio is adjusted for each of the four options so that the reference frequency selected by REFSEL0 and REFSEL1 is the same for all operating modes. To ensure the TXSCLK frequency is accurate enough to operate in a SONET system, the REFCLK input must be generated from a differential PECL crystal oscillator with a frequency accuracy better than 4.6 ppm for compliance with “ITU G.813 (option 1)”, or 20 ppm for “ITU G.813 (option 2)”. The maximum value specified for reference clock jitter must be guaranteed over the a 12 kHz to 1 MHz bandwidth in order to comply with SONET jitter requirements (see Table 4). The on-chip PLL contains a phase detector, a loop filter and a VCO. The phase detector compares the phases of the output and REFCLK input signals. The loop filter converts the phase detector output into a smooth DC voltage that is used to vary the VCO frequency. The VCO control voltage generated by the loop filter is referenced to the average DC level in the output pulse train generated by the phase discriminator. The corner frequency is optimized to minimize output phase jitter. Table 3 Reference frequency options Table 4 Reference jitter limits TIMING GENERATOR The timing generator performs two functions. It provides a byte rate version of the TXSCLK along with a mechanism for phase aligning the incoming byte clock and the clock that loads the parallel-to-serial shift register. REFSEL0 REFSEL1 INPUT CLOCK FREQUENCY 0 0 19.44 MHz 0 1 38.88 MHz 1 0 51.84 MHz 1 1 77.76 MHz MAXIMUM REFERENCE CLOCK JITTER IN 12 kHz TO 1 MHz BAND OPERATING MODE 84 ps (p-p) STM4/OC12 336 ps (p-p) STM1/OC3 The SYNCLKDIV output is a byte rate version of TXSCLK. For STM4/OC12, the SYNCLKDIV frequency is 77.76 or 155.52 MHz and for STM1/OC3, it is 19.44 or 38.88 MHz. SYNCLKDIV is intended for use as a byte speed clock for upstream multiplexing and overhead processing circuits. Using SYNCLKDIV for upstream circuits will ensure a stable frequency and phase relationship is maintained between the data entering and leaving the TZA3005. For parallel-to-serial conversion, the parallel input data is transferred from the TXPCLK byte clock timing domain to the internally generated byte clock timing domain, which is phase aligned to TXPCLK. The timing generator also produces a feedback reference clock for the clock synthesizer. A counter divides the synthesized clock down to the same frequency as the reference clock REFCLK. The PLL in the clock synthesizer maintains the stability of the synthesized clock by comparing the phase of the feedback reference clock with that of the reference clock (REFCLK). The modulus of the counter is a function of the reference clock frequency and the operating frequency. PARALLEL-TO-SERIAL CONVERTER The parallel-to-serial converter shown in Fig.1 contains two byte-wide registers. The first register latches the data from the parallel bus (TXPD0 to TXPD7) on the rising edge of TXPCLK. The second register is a parallel loading shift register which takes its input from the first register. The parallel data transfer is controlled by an internally generated byte clock, which is phase aligned with the transmit serial clock (see Section “Timing generator”). The TXSCLK signal is used to shift the serial data out of the second register. Receiver operation The TZA3005 transceiver chip performs the first stage in the digital processing of a STM1/OC3 or STM4/OC12 serial bitstream. It converts the 155.52 or 622.08 Mbits/s data stream into a 19.44 or 77.76 Mbytes/s serial format. In nibble mode, a parallel data stream of 38.88 or 155.52 MHz is generated. Diagnostic (transmitter to receiver) and line (receiver to transmitter) loopback modes are provided. FRAME AND BYTE BOUNDARY DETECTION The frame and byte boundary detection circuitry searches the incoming data for three consecutive A1 bytes followed immediately by three consecutive A2 bytes. Framing |
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