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IDT70V657S12BF Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT70V657S12BF Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 24 page  IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges 6 Pin Names NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on I/OX. 2. OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 3. Addresses A16x is a NC for IDT70V658. Also, Addresses A16x and A15x are NC's for IDT70V657. 4. BUSY is an input as a slave (M/S = VIL). Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables - (Input) R/WL R/WR Read/Write Enable - (Input) OEL OER Output Enable - (Input) A0L - A16L(3) A0R - A16R(3) Address - (Input) I/O0L - I/O35L I/O0R - I/O35R Data Input/Output SEML SEMR Semaphore Enable - (Input) INTL INTR Interrupt Flag - (Output) BUSYL BUSYR Busy Flag - (Output)(4) BE0L - BE3L BE0R - BE3R Byte Enables (9-bit bytes) - (Input) VDDQL VDDQR Power (I/O Bus) (3.3V or 2.5V) - (Input)(1) OPTL OPTR Option for selecting VDDQX - (Input)(1,2) M/S Master or Slave Select - (Input) VDD Power (3.3V) - (Input)(1) VSS Ground (0V) - (Input) TDI Test Data Input TDO Test Data Output TCK Test Logic Clock (10MHz) TMS Test Mode Select TRST Reset (Initialize TAP Controller) 4869 tbl 01 |
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