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EL5126CL-T13 Datasheet(PDF) 8 Page - Intersil Corporation |
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EL5126CL-T13 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 11 page 8 I2C Timing Diagram 2 Analog Section TRANSFER FUNCTION The transfer function is: where data is the decimal value of the 10-bit data binary input code. The output voltages from the EL5126 will be derived from the reference voltages present at the VREFL and VREFH pins. The impedance between those two pins is about 32k Ω. Care should be taken that the system design holds these two reference voltages within the limits of the power rails of the EL5126. GND < VREFH ≤ VS and GND ≤ VREFL ≤ VREFH. In some LCD applications that require more than 8 channels, the system can be designed such that one EL5126 will provide the Gamma correction voltages that are more positive than the VCOM potential. The second EL5126 can provide the Gamma correction voltage more negative than the VCOM potential. The Application Drawing shows a system connected in this way. CLOCK OSCILLATOR The EL5126 requires an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn’t be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs. This clock may be input or output via the clock pin labeled OSC. The internal clock is provided by an internal oscillator running at approximately 21kHz and can be output to the OSC pin. In a 2 chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the OSC pin will output the clock from the internal oscillator. The second chip may have the OSC pin connected to this clock source. For transient load application, the external clock Mode should be used to ensure all functions are synchronized together. The positive edge of the external clock to the OSC pin should be timed to avoid the transient load effect. The Application Drawing shows the LCD H rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. After power on, the chip will start with the internal oscillator mode. At this time, the OSC pin will be in a high impedance condition to prevent contention. By setting pin 32 to high, the chip is on external clock mode. Setting pin 32 to low, the chip is on internal clock mode. tR tF tS tH tS tH tR tF START CONDITION STOP CONDITION DATA CLOCK START, STOP & TIMING DETAILS OF I2C INTERFACE V OUT IDEAL ) ( V REFL = data 1024 ------------- V REFH - VREFL () × + EL5126 |
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