9

ATA5756/ATA5757

4702H–RKE–09/04

Accuracy of the Center

Frequency

The imaginary part of the impedance in large signal steady state oscillation IM

into the pin 7 (XTO1), causes some additional frequency tolerances, due to pulling of

the XTO oscillation frequency. These tolerances have to be added to the tolerances of

the crystal itself (adjustment tolerance, temperature stability and ageing) and the influ-

ence to the center frequency due to tolerances of C

value of IM

by using a crystal with known frequency and choosing C

ter frequency equals the crystal frequency, and the frequency deviation is as expected.

Then, from the nominal value, the IM

P = -IM

quency tolerance of P = ±16.86 ppm results. If using crystals with other C

additional frequency tolerance can be calculated in the same way. For example, a lower

C

C

CLK Output

An output CLK signal of 1.64 MHz (ATA5756 operating at 315 MHz) and 1.69 MHz

(ATA5757 operating at 433.92 MHz) is provided for a connected microcontroller. The

delivered signal is CMOS-compatible with a High and Low time of >125 ns if the load

capacitance is lower than 20 pF. The CLK output is Low in power-down mode due to an

internal pull-down resistor. After enabling the PLL and XTO the signal stays Low until

the amplitude of the crystal oscillator has reached 35% to 80% of its amplitude. Then,

the CLK output is activated synchronously with its output signal so that the first period of

the CLK output signal is a full period.

Clock Pulse Take-over by

Microcontroller

The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s

ATARx9x microcontroller family provides the special feature of starting with an inte-

grated RC oscillator to switch on the ATA5756/ATA5757’s external clocking and to wait

automatically until the CLK output of the ATA5756/ATA5757 is activated. After a time

period of 250 µs the message can be sent with crystal accuracy.

Output Matching and Power

Setting

The output power is set by the load impedance of the antenna. The maximum output

power is achieved with a load impedance of Z

315 MHz and Z

to V

The power amplifier delivers a current pulse and the maximum output power is delivered

to a resistive load if the 0.66 pF output capacitance of the power amplifier is compen-

sated by the load impedance.

At the ANT1 pin, the RF output amplitude is about V

The load impedance is defined as the impedance seen from the ATA5756’s ANT1,

ANT2 into the matching network. Do not mix up this large-signal load impedance with a

small-signal input impedance delivered as an input characteristic of RF amplifiers.

The latter is measured from the application into the IC instead of from the IC into the

application for a power amplifier.

The 0.66 pF output capacitance absorbed into the load impedance a real impedance of

684

Ω (ATA5756) at 315 MHz and 623 Ω (ATA5757) at 433.92 MHz should be mea-

sured with a network analyses at pin 5 (ANT1) with the ATA5756/ATA5757 soldered, an

optimized antenna connected and the power amplifier switched off.

Less output power is achieved by lowering the real parallel part where the parallel imag-

inary part should be kept constant. Lowering the real part of the load impedance also

reduces the supply voltage dependency of the output power.