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X80120Q20I Datasheet(PDF) 11 Page - Intersil Corporation |
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X80120Q20I Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 17 page  11 FN8151.0 January 20, 2005 Control Registers and Memory The user addressable internal control, status and memory components of the X80120 can be split up into three parts: • Control Register (CR) • Fault Detection Register (FDR) • EEPROM array Registers The Control Registers and Fault Detection Register are summarized in Table 4. Changing bits in these registers change the operation of the device or clear fault conditions. Reading bits from these registers provides information about device configuration or fault conditions. Reads and writes are done through the SMBus serial port. All of the Control Register bits are nonvolatile (except for the WEL bit), so they do not change when power is removed. The values of the Register Block can be read at any time by performing a random read (see Serial Interface) at the specific byte address location. Only one byte is read by each register read operation. Bits in the registers can be modified by performing a single byte write operation directly to the address of the register and only one data byte can change for each register write operation.EEPROM Array. The X80120 contains a 2kbit EEPROM memory array. This array can contain information about manufacturing location and dates, board configuration, fault conditions, service history, etc. Access to this memory is through the SMBus serial port. Read and write operations are similar to those of the control registers, but a single command can write up to 16 bytes at one time. A single read command can return the entire contents of the EEPROM memory. Register and Memory Protection In order to reduce the possibility of inadvertent changes to either a control register of the contents of memory, several protection mechanisms are built into the X80120. These are a Write Enable Latch, Block Protect bits, a Write Protect Enable bit and a Write Protect pin. WEL: Write Enable Latch A write enable latch (WEL) bit controls write accesses to the nonvolatile registers and the EEPROM memory array in the X80120. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address (registers or memory) will be ignored. The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register 0 (CR0). It is important to write only 00h or 80h to the CR0 register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Note, a write to FDR or RSR does not require that WEL=1. BP1 and BP0: Block Protect Bits The Block Protect Bits, BP1 and BP0, determines which blocks of the memory array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of four segments of the array. WPEN: Write Protect Enable The Write Protect pin and Write Protect Enable bit in the CR1 register control the Programmable Hardware Write Protect feature. Hardware Protection is enabled when the WP pin is HIGH and WPEN bit is HIGH and disabled when WP pin is LOW or the WPEN bit is LOW. When the chip is Hardware Write Protected, non-volatile writes to all control registers (CR1, CR2, and CR3) are disabled including BP bits, the WPEN bit itself, and the blocked sections in the memory Array. Only the section of the memory array that are not block protected can be written. Non Volatile Programming Voltage (VP) Nonvolatile writes require that a programming voltage be applied to the VP for the duration of a nonvolatile write operation. PROTECTED ADDRESSES (SIZE) ARRAY LOCK 0 0 None (Default) None (Default) 0 1 C0h - FFh (64 bytes) Upper 1/4 1 0 80h - FFh (128 bytes) Upper 1/2 1 1 00h - FFh (256 bytes) All TABLE 3. WRITE PROTECT CONDITIONS WEL WP WPEN MEMORY ARRAY NOT BLOCK PROTECTED MEMORY ARRAY BLOCK PROTECTED WRITES TO CR1, CR2, CR3 PROTECTION LOW X X Writes Blocked Writes Blocked Writes Blocked Hardware HIGH LOW X Writes Enabled Writes Blocked Writes Enabled Software HIGH X LOW Writes Enabled Writes Blocked Writes Enabled Software HIGH HIGH HIGH Writes Enabled Writes Blocked Writes Blocked Hardware X80120, X80121 |
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