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X40431V14I-A Datasheet(PDF) 7 Page - Intersil Corporation |
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X40431V14I-A Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 24 page 7 FN8251.0 July 29, 2005 Figure 6. VTRIPX Set/Reset Sequence (X = 1, 2, 3) WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a vola- tile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a high volt- age write cycle, so the device is ready for the next operation immediately after the stop condition. BP: Block Protect Bits (Nonvolatile) The Block Protect Bit BP, determines which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bit will prevent write operations to half or none of the array. VTRIPX Programming Apply VCC and Voltage Decrease VX Actual VTRIPX - Desired VTRIPX DONE Set Higher VX Sequence Error < MDE– | Error | < | MDE | YES NO Error > MDE+ > Desired VTRIPX to VX Desired Present Value VTRIPX< Execute No YES Execute VTRIPX Reset Sequence Set VX = desired VTRIPX New VX applied = Old VX applied + | Error | New VX applied = Old VX applied - | Error | Execute Reset VTRIPX Sequence Output Switches? Note: X = 1, 2, 3 Let: MDE = Maximum Desired Error Vx = VCC, VxMON MDE+ Desired Value MDE– Acceptable Error Range Error = Actual - Desired BP Protected Addresses (Size) Memory Array Lock 0 None None 1 100h – 1FFh (256 bytes) Upper Half of Memory Array X40430, X40431, X40434, X40435 |
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