7

FN8250.0

July 29, 2005

Write Cycle Limits

the device requires to automatically complete the internal write operation.

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write

cycle. During the write cycle, the X45620 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the

device does not respond to its slave address.

Write Cycle Timing

SCL

SDA IN

Slave Address Byte

Clk 1

Clk 9

Symbol

Parameter

Min

Max

Unit

Test Conditions

Write Cycle Time

—

5

10

ms

Note 4

SCL

SDA

Word n

ACK

Stop

Condition

Start

Condition

X45620