X40420 datasheet(11/25 Pages) INTERSIL

Part #	X40420

Description	Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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11

March 28, 2005

Figure 10. Byte Write Sequence

Page Write

The device is capable of a page write operation. It is

initiated in the same manner as the byte write opera-

tion; but instead of terminating the write cycle after the

first data byte is transferred, the master can transmit

an unlimited number of 8-bit bytes. After the receipt of

each byte, the device will respond with an acknowl-

edge, and the address is internally incremented by

one. The page address remains constant. When the

counter reaches the end of the page, it “rolls over” and

goes back to ‘0’ on the same page.

This means that the master can write 16 bytes to the

page starting at any location on that page. If the master

begins writing at location 10, and loads 12 bytes, then

the first 6 bytes are written to locations 10 through 15,

and the last 6 bytes are written to locations 0 through 5.

Afterwards, the address counter would point to location

6 of the page that was just written. If the master sup-

plies more than 16 bytes of data, then new data over-

writes the previous data, one byte at a time.

Figure 11. Page Write Operation

Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.

The master terminates the Data Byte loading by issuing

a stop condition, which causes the device to begin the

nonvolatile write cycle. As with the byte write operation,

all inputs are disabled until completion of the internal

write cycle. See Figure 11 for the address, acknowl-

edge, and data transfer sequence.

S

t

a

r

t

S

t

o

p

Slave

Address

Byte

Address

Data

A

C

K

A

C

K

A

C

K

SDA Bus

Signals from

the Slave

Signals from

the Master

0

S

t

a

r

t

S

t

o

p

Slave

Address

Byte

Address

Data

(n)

A

C

K

A

C

K

A

C

K

SDA Bus

Signals from

the Slave

Signals from

the Master

0

Data

(1)

A

C

K

(1

≤ n ≤ 16)

10 1

0

address

10

6 Bytes

n-1

6 Bytes

address

= 5

address pointer

ends here

Addr = 6

X40420, X40421

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