X40030S14-C datasheet(7/21 Pages) INTERSIL

Part #	X40030S14-C

Description	Triple Voltage Monitor with Intergrated CPU Supervisor

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Manufacturer	INTERSIL [Intersil Corporation]

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7

FN8114.0

April 28, 2005

Figure 6. VTRIPX Set/Reset Sequence (X = 1, 2, 3)

WEL: Write Enable Latch (Volatile)

The WEL bit controls the access to the memory and to

the Register during a write operation. This bit is a vola-

tile latch that powers up in the LOW (disabled) state.

While the WEL bit is LOW, writes to any address,

including any control registers will be ignored (no

acknowledge will be issued after the Data Byte). The

WEL bit is set by writing a “1” to the WEL bit and

zeroes to the other bits of the control register.

Once set, WEL remains set until either it is reset to 0

(by writing a “0” to the WEL bit and zeroes to the other

bits of the control register) or until the part powers up

again. Writes to the WEL bit do not cause a high volt-

age write cycle, so the device is ready for the next

operation immediately after the stop condition.

PUP1, PUP0: Power Up Bits (Nonvolatile)

The Power Up bits, PUP1 and PUP0, determine the

tPURST time delay. The nominal power up times are

shown in the following table.

VTRIPX Programming

Apply VCC and Voltage

Decrease VX

Actual VTRIPX -

Desired VTRIPX

DONE

Set Higher VX Sequence

Error < MDE–

| Error | < | MDE |

YES

NO

Error > MDE+

> Desired VTRIPX to VX

Desired

Present Value

VTRIPX<

Execute

No

YES

Execute

VTRIPX Reset Sequence

Set VX = desired VTRIPX

New VX applied =

Old VX applied + | Error |

New VX applied =

Old VX applied - | Error |

Execute Reset VTRIPX

Sequence

Output Switches?

Note: X = 1, 2, 3

Let: MDE = Maximum Desired Error

Vx = VCC, VxMON

MDE+

Desired Value

MDE–

Acceptable

Error Range

Error = Actual - Desired

PUP1

PUP0

Power on Reset Delay (tPURST)

0

50ms

0

1

200ms (factory setting)

1

0

400ms

1

800ms

X40030, X40031, X40034, X40035

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X40030S14-C Datasheet(PDF) 7 Page - Intersil Corporation

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