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X40233 Datasheet(PDF) 11 Page - Intersil Corporation |
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X40233 Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 36 page 11 FN8115.0 April 11, 2005 At both ends of each array and between each resistor segment there is a CMOS switch connected between the resistor array and the wiper (Rwx) output. Within each individual array, only one switch may be turned on at any one time. These switches are controlled by the Wiper Counter Register (WCR) (See Figure 6). The WCR is a volatile register. On power-up of the X4023x, wiper position data is au- tomatically loaded into the WCR from its associated Non Volatile Memory (NVM) Register. The Table below shows the Initial Values of the DCP WCR’s before the contents of the NVM is loaded into the WCR. The data in the WCR is then decoded to select and enable one of the respective FET switches. A “make before break” sequence is used internally for the FET switches when the wiper is moved from one tap posi- tion to another. Hot Pluggability Figure 7 shows a typical waveform that the X4023x might experience in a Hot Pluggable situation. On power-up, VCC applied to the X4023x may exhibit some amount of ringing, before it settles to the required value. The device is designed such that the wiper terminal (RWx) is recalled to the correct position (as per the last stored in the DCP NVM), when the voltage applied to VCC exceeds VTRIP1 for a time exceeding tPURST (the Power-on Reset time, set in the CR Register - See “CONTROL AND STATUS REGISTER” on page 18.). Therefore, if ttrans is defined as the time taken for VCC to settle above VTRIP1 (Figure 7): then the desired wiper terminal position is recalled by (a maximum) time: ttrans + tPURST. It should be noted that ttrans is determined by system hot plug conditions. DCP Operations In total there are three operations that can be per- formed on any internal DCP structure: —DCP Nonvolatile Write —DCP Volatile Write —DCP Read ACK returned? Issue Slave Address Byte (Read or Write) Byte load completed by issuing STOP. Enter ACK Polling Issue STOP Issue START NO YES High Voltage Cycle complete. Continue command sequence? Issue STOP NO Continue normal Read or Write command sequence PROCEED YES Figure 5. Acknowledge Polling Sequence DECODER RESISTOR ARRAY RHx FET SWITCHES RWx 0 1 2 N WIPER REGISTER COUNTER NON MEMORY VOLATILE (WCR) (NVM) “WIPER” Figure 6. DCP Internal Structure DCP Initial Values Before Recall R0 (64 TAP) VH (TAP = 63) R1 (100 TAP) VL (TAP = 0) R2 (256 TAP) VH (TAP = 255) X40231, X40233, X40235, X40237, X40239 |
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