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4 FN8115.0 April 11, 2005 X40233 PIN ASSIGNMENT SOIC Name Function 1NC No Connect 2NC No Connect 3V3MON V3MON Voltage Monitor Input. V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than the VTRIP3 threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to VSS when not used. 4V3FAIL V3MON RESET Output. This open drain output makes a transition to a HIGH level when V3MON is greater than VTRIP3 and goes LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires the use of an external “pull-up” resistor. 5MR Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET pin (VCC RESET Output pin). RESET will remain HIGH for time tPURST after MR has returned to it’s normally LOW state. The reset time can be selected using bits PUP1 and PUP0 in the CR Register. The MR pin requires the use of an external “pull-down” resistor. 6WP Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled. 7SCL Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output. 8SDA Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor. 9 VSS Ground. 10 RW1 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP. 11 RH1 Connection to end of resistor array for (the 100 Tap) DCP. 12 NC No Connect 13 V2MON V2MON Voltage Monitor Input. V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than the VTRIP2 threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to VSS when not used. 14 V2FAIL V2MON RESET Output. This open drain output makes a transition to a HIGH level when V2MON is greater than VTRIP2, and goes LOW when V2MON is less than VTRIP2. There is no power-up reset delay circuitry on this pin. The V2FAIL pin requires the use of an external “pull-up” resistor. 15 RESET VCC RESET Output. This is an active HIGH, open drain output which becomes active whenever VCC falls below VTRIP1. RESET becomes active on power-up and remains active for a time tPURST after the power supply stabilizes (tPURST can be changed by varying the PUP0 and PUP1 bits of the internal control register). The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active (HIGH) using the manual reset (MR) input pin. 16 VCC Supply Voltage. X40231, X40233, X40235, X40237, X40239 |
