X9440YP24-2.7 datasheet(7/21 Pages) INTERSIL

Part #	X9440YP24-2.7

Description	Mixed Signal with SPI Interface

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Manufacturer	INTERSIL [Intersil Corporation]

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7

FN8200.0

March 28, 2005

Figure 6. Three-Byte Command Sequence (Read)

Figure 7. Increment/Decrement Command Sequence

Increment/Decrement

The final command is Increment/Decrement. It is differ-

ent from the other commands, because it’s length is

indeterminate. Once the command is issued, the mas-

ter can clock the selected wiper up and/or down in one

resistor segment steps; thereby, providing a fine tuning

capability to the host. For each SCK clock pulse (tHIGH)

while SI is HIGH, the selected wiper will move one

resistor segment towards the VH terminal. Similarly, for

each SCK clock pulse while SI is LOW, the selected

wiper will move one resistor segment towards the VL

terminal. A detailed illustration of the sequence and tim-

ing for this operation are shown in Figure 7 and 8.

Write in Process

The contents of the data registers are saved to nonvol-

atile memory when the CS pin goes from LOW to

HIGH after a complete write sequence is received by

the device. The progress of this internal write opera-

tion can be monitored by a write in process bit (WIP).

The WIP bit is read with a read status command.

Figure 8. Increment/Decrement Timing Limits

0

1

0

1

A1 A0

I3

I2

I1

I0

R1 R0 P1 P0

SCL

SI

CS

00

S0

0

D5 D4 D3 D2

D1 D0

Don’t Care

0

101

00

A1 A0

I3

I2

I1

I0

0

P1

P0

SCK

SI

I

N

C

1

I

N

C

2

I

N

C

n

D

E

C

1

D

E

C

n

0

CS

SCK

SI

VW

INC/DEC CMD Issued

Voltage Out

tWRID

X9440

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X9440YP24-2.7 Datasheet(PDF) 7 Page - Intersil Corporation

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