X9448YV24I datasheet(5/19 Pages) INTERSIL

Part #	X9448YV24I

Description	Mixed Signal with 2-Wire Interface

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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5 / 19 page

5

FN8201.0

April 18, 2005

or analog control register is essentially a write to a

static RAM. The response of the wiper to this action

will be delayed tSTPWV. A transfer from the Wiper

Counter Register current wiper position to a data reg-

ister is a write to nonvolatile memory and takes a mini-

mum of tWR to complete. The transfer can occur

between one of the two potentiometers or one of the

two voltage comparators and one of its associated

registers; or it may occur globally, wherein the transfer

occurs between both of the potentiometers and volt-

age comparators and one of their associated registers.

Four instructions require a three-byte sequence to com-

plete. The basic sequence is illustrated in Figure 4.

These instructions transfer data between the host and

the X9448; either between the host and one of the data

registers or directly between the host and the wiper

counter and analog control registers. These instructions

are: read wiper counter register or analog control regis-

ter, read the current wiper position of the selected pot or

the comparator control bits, Write wiper counter register

or analog control register, i.e. change current wiper

position of the selected pot or control the voltage com-

parator; read data register, read the contents of the

selected nonvolatile register; write data register, write a

new value to the selected data register. The bit struc-

tures of the instructions are shown in Figure 6.

The increment/decrement command is different from

the other commands. Once the command is issued

and the X9448 has responded with an acknowledge,

the master can clock the selected wiper up and/or

down in one segment steps; thereby, providing a fine

tuning capability to the host. For each SCL clock pulse

(tHIGH) while SDA is HIGH, the selected wiper will

move one resistor segment towards the VH terminal.

Similarly, for each SCL clock pulse while SDA is LOW,

the selected wiper will move one resistor segment

towards the VL terminal. A detailed illustration of the

sequence for this operation is shown in Figure 5.

Figure 3. Two-Byte Command Sequence

Figure 4. Three-Byte Command Sequence

Figure 5. Increment/Decrement Command Sequence

S

T

A

R

T

0101

A3

A2

A1

A0

A

C

K

I3

I2

I1

I0

R1

R0

P1 P0

A

C

K

SCL

SDA

S

T

O

P

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0 A

C

K

I3

I2

I1 I0

P1 P0 R1 R0 A

C

K

SCL

SDA

S

T

O

P

A

C

K

D5 D4 D3 D2

D1 D0

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3

I2

I1

I0

P1 P0 R1 R0

A

C

K

SCL

SDA

S

T

O

P

X

I

N

C

1

I

N

C

2

I

N

C

n

D

E

C

1

D

E

C

n

X9448

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