X9251TV24-2.7 datasheet(4/22 Pages) INTERSIL

Part #	X9251TV24-2.7

Description	Single Supply/Low Power/256-Tap/SPI Bus

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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4

FN8166.2

September 14, 2005

PIN DESCRIPTIONS

Bus Interface Pins

SERIAL OUTPUT (SO)

SO is a serial data output pin. During a read cycle,

data is shifted out on this pin. Data is clocked out by

the falling edge of the serial clock.

SERIAL INPUT (SI)

SI is the serial data input pin. All opcodes, byte

addresses and data to be written to the device

registers are input on this pin. Data is latched by the

rising edge of the serial clock.

SERIAL CLOCK (SCK)

The SCK input is used to clock data into and out of the

X9251.

HOLD (HOLD)

HOLD is used in conjunction with the CS pin to select

the device. Once the part is selected and a serial

sequence is underway, HOLD may be used to pause

the serial communication with the controller without

resetting the serial sequence. To pause, HOLD must

be brought LOW while SCK is LOW. To resume

communication, HOLD is brought HIGH, again while

SCK is LOW. If the pause feature is not used, HOLD

should be held HIGH at all times.

DEVICE ADDRESS (A1 - A0)

The address inputs are used to set the two least

significant bits of the slave address. A match in the

slave address serial data stream must be made with

the address input in order to initiate communication

with the X9251. Device pins A1 - A0 must be tie to a

logic level which specify the internal address of the

device, see Figures 2, 3, 4, 5 and 6.

CHIP SELECT (CS)

When CS is HIGH, the X9251 is deselected and the

SO pin is at high impedance, and (unless an internal

write cycle is underway) the device is in the standby

state. CS LOW enables the X9251, placing it in the

active power mode. It should be noted that after a

power-up, a HIGH to LOW transition on CS is required

prior to the start of any operation.

Potentiometer Pins

RH, RL

The RH and RL pins are equivalent to the terminal

connections on a mechanical potentiometer. Since

there are 4 potentiometers, there are 4 sets of RH and

RL such that RH0 and RL0 are the terminals of DCP0

and so on.

RW

The wiper pin are equivalent to the wiper terminal of a

mechanical

potentiometer.

Since

there

are

4

potentiometers, there are 4 sets of RW such that RW0

is the terminals of DCP0 and so on.

Supply Pins

SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY

GROUND (VSS)

The VCC pin is the system supply voltage. The VSS

pin is the system ground.

Other Pins

NO CONNECT

No connect pins should be left floating. This pins are

used for Intersil manufacturing and testing purposes.

HARDWARE WRITE PROTECT INPUT (WP)

The WP pin when LOW prevents non-volatile writes to

the Data Registers.

PRINCIPLES OF OPERATION

The X9251 is an integrated circuit incorporating four

DCPs and their associated registers and counters,

and a serial interface providing direct communication

between a host and the potentiometers.

DCP Description

Each DCP is implemented with a combination of

resistor elements and CMOS switches. The physical

ends of each DCP are equivalent to the fixed terminals

of a mechanical potentiometer (RH and RL pins). The

RW pin is an intermediate node, equivalent to the

wiper terminal of a mechanical potentiometer.

The position of the wiper terminal within the DCP is

controlled by an 8-bit volatile Wiper Counter Register

(WCR).

X9251

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X9251TV24-2.7 Datasheet(PDF) 4 Page - Intersil Corporation

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