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X9259US24-2.7 Datasheet(PDF) 7 Page - Intersil Corporation |
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X9259US24-2.7 Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 21 page  7 FN8169.2 September 16, 2005 Identification Byte The first byte sent to the X9259 from the host is called the Identification Byte. The most significant four bits are a Device Type Identifier, ID[3:0] bits, which must be 0101. Refer to Table 3. Only the device which Slave Address matches the incoming device address sent by the master executes the instruction. The A3 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE (I) The next byte sent to the X9259 contains the instruction and register pointer information. The four most significant bits are used provide the instruction opcode I [3:0]. The RB and RA bits point to one of the four data registers of each associated XDCP. The least two significant bits point to one of four Wiper Counter Registers or DCPs. The format is shown in Table 4. Data Register Selection #: 0, 1, 2, or 3 The least significant four bits of the Identification Byte are the Slave Address bits, AD[3:0]. To access the X9259, these four bits must match the logic values of pins A3, A2, A1, and A0. SDA SCL START DATA DATA STOP STABLE CHANGE DATA STABLE FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS SDA Output from Transmitter SDA Output from Receiver 8 1 9 START ACK SCL from Master FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER REGISTER RB RA DR#0 0 0 DR#1 0 1 DR#2 1 0 DR#3 1 1 X9259 |
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