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X9271TVI-2.7 Datasheet(PDF) 7 Page - Intersil Corporation |
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X9271TVI-2.7 Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 22 page 7 FN8174.1 March 31, 2005 DEVICE DESCRIPTION Instructions IDENTIFICATION BYTE (ID AND A) The first byte sent to the X9271 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device id for the X9271; this is fixed as 0101[B] (refer to Table 4). The A1 - A0 bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A1 - A0 input pins. The slave address is externally specified by the user. The X9271 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9271 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A1 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE (I[3:0]) The next byte sent to the X9271 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (I[3:0]). The RB and RA bits point to one of the four Data Registers. P0 is the POT selection; since the X9271 is single POT, the P0=0. The format is shown in Table 5. REGISTER BANK SELECTION (R1, R0, P1, P0) There are 16 registers organized into four banks. Bank 0 is the default bank of registers. Only Bank 0 registers can be used for data register to Wiper Counter Register operations. Banks 1, 2, and 3 are additional banks of registers (12 total) that can be used for SPI write and read operations. The data registers in Banks 1, 2, and 3 cannot be used for direct read/write operations between the Wiper Counter Register. Register Selection (DR0 to DR3) Table Register Bank Selection (Bank 0 to Bank 3) Table Table 4. Identification Byte Format RB RA Register Selection Operations 0 0 0 Data Register Read and Write; Wiper Counter Register Operations 0 1 1 Data Register Read and Write; Wiper Counter Register Operations 1 0 2 Data Register Read and Write; Wiper Counter Register Operations 1 1 3 Data Register Read and Write; Wiper Counter Register Operations P1 P0 Bank Selection Operations 0 0 0 Data Register Read and Write; Wiper Counter Register Operations 0 1 1 Data Register Read and Write Only 1 0 2 Data Register Read and Write Only 1 1 3 Data Register Read and Write Only ID3 ID2 ID1 ID0 0 0 A1 A0 0101 (MSB) (LSB) Device Type Identifier Set to 0 for proper operation Internal Slave Address X9271 |
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