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X9271UV-2.7 Datasheet(PDF) 8 Page - Intersil Corporation |
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X9271UV-2.7 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 22 page 8 FN8174.1 March 31, 2005 Table 5. Instruction Byte Format DEVICE DESCRIPTION Instructions Five of the eight instructions are three bytes in length. These instructions are: – Read Wiper Counter Register – read the current wiper position of the potentiometer; – Write Wiper Counter Register – change current wiper position of the potentiometer; – Read Data Register – read the contents of the selected Data Register; – Write Data Register – write a new value to the selected Data Register. – Read Status - This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The basic sequence of the three byte instructions is illustrated in Figure 3. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. The Read Status Register instruction is the only unique format (See Figure 4). Two instructions require a two-byte sequence to complete (Figure 2). These instructions transfer data between the host and the X9271; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: – XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. The final command is Increment/Decrement (Figure 5 and 6). It is different from the other commands, because it’s length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instruction format for more details. Write in Process (WIP bit) The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command. I3 I2 I1 P0 RB RA P1 P0 (MSB) (LSB) Instruction Opcode Register Selection Pot Selection (WCR Selection) Set to P0=0 for potentiometer operations P1 and P0 are used also for register Bank Selection for SPI Register Write and Read operations X9271 |
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