11

FN8164.1

September 15, 2005

correct recall of the wiper registers)

The preferred power-on sequence is as follows: First Vcc,

then the potentiometer pins. It is suggested that Vcc reach

90% of its final value before power is applied to the

potentiometer pins. The Vcc ramp rate specification should

be met, and any glitches or slope changes in the Vcc line

should be held to <100mV if possible. Also, Vcc should not

reverse polarity by more than 0.5V.

Notes: (5) This parameter is guaranteed by characterization or sample testing.

guaranteed by design.

(7) This parameter is guaranteed by design.

(8) Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve.

(9) Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse

width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to

the device.

Symbol Table

Endurance and Data Retention

PARAMETER

MIN

UNIT

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

Years

Capacitance

SYMBOL

PARAMETER

TEST CONDITION

MAX

UNIT

Input/output capacitance (SDA)

19

pF

Input capacitance (A0, A1, A2, A3 and SCL)

12

pF

Power-up Timing

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

Power-up to initiation of read operation

1

ms

Power-up to initiation of write operation

5

ms

0.2

50

V/msec

AC Conditions of Test

Input pulse levels

Input rise and fall times

10ns

Input and output timing levels

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

X9241A