1

®

FN8166.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

X9251

Single Supply/Low Power/256-Tap/SPI Bus

Quad Digitally-Controlled (XDCP™)

Potentiometer

FEATURES

• Four potentiometers in one package

• 256 resistor taps–0.4% resolution

• SPI Serial Interface for write, read, and transfer

operations of the potentiometer

• Wiper resistance: 100

• 4 Non-volatile data registers for each

potentiometer

• Non-volatile storage of multiple wiper positions

• Standby current < 5µA max

•50k

Ω, 100kΩ versions of total resistance

• 100 yr. data retention

• Single supply version of X9250

• Endurance: 100,000 data changes per bit per

register

• 24 Ld SOIC, 24 Ld TSSOP

• Low power CMOS

• Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X9251 integrates four digitally controlled potentio-

meters (XDCP) on a monolithic CMOS integrated

circuit.

The digitally controlled potentiometers are imple-

mented with a combination of resistor elements and

CMOS switches. The position of the wipers are

controlled by the user through the SPI bus interface.

Each potentiometer has associated with it a volatile

Wiper Counter Register (WCR) and four non-volatile

Data Registers that can be directly written to and read

by the user. The content of the WCR controls the

position of the wiper. At power-up, the device recalls

the content of the default Data Registers of each DCP

(DR00, DR10, DR20, and DR30) to the corresponding

WCR.

The

XDCP

can

be

used

as

a

three-terminal

potentiometer or as a two terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

POWER UP,

INTERFACE

CONTROL

AND

SPI

DCP0

A1

SO

SI

CS

HOLD

SCK

WP

WCR0

DR00

DR01

DR02

DR03

DCP1

WCR1

DR10

DR11

DR12

DR13

DCP2

WCR2

DR20

DR21

DR22

DR23

DCP3

WCR3

DR30

DR31

DR32

DR33

A0

Interface

STATUS

Data Sheet

September 14, 2005