X9252TV24I-2.7 datasheet(11/19 Pages) INTERSIL

Part #	X9252TV24I-2.7

Description	Low Power Quad 256-Tap 2-Wire Bus Up/Down Interface

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Manufacturer	INTERSIL [Intersil Corporation]

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11

FN8167.1

September 14, 2005

Nonvolatile Write Acknowledge Polling

After a nonvolatile write command sequence is correctly

issued (including the final STOP condition), the X9252

initiates an internal high voltage write cycle. This cycle

typically requires 5ms. During this time, any Read or Write

command is ignored by the X9252. Write Acknowledge

Polling is used to determine whether a high voltage write

cycle is completed.

During acknowledge polling, the master first issues a START

condition followed by a Slave Address Byte. The Slave

Address Byte contains the X9252’s Device Type Identifier

and Device Address. The LSB of the Slave Address (R/W)

can be set to either 1 or 0 in this case. If the device is busy

within the high voltage cycle, then no ACK is returned. If the

high voltage cycle is completed, an ACK is returned and the

master can then proceed with a new Read or Write

operation. (Refer to figure 5.)

2-Wire Serial Interface Operation

X9252 Digital Potentiometer Register Organization

Refer to the Functional Diagram on page 2. There are four

Digitally Controlled Potentiometers, referred to as DCPi,

i=0,1,2,3. Each potentiometer has one volatile Wiper Control

Register (WCR) with the corresponding number, WCRi,

i=0,1,2,3. Each potentiometer also has four nonvolatile

registers to store wiper position or general data, these are

numbered DRi0, DRi1, DRi2 and DRi3, i=0,1,2,3.

The registers are organized in five pages of four, with one

page consisting of the WCRi (i=0-3), a second page

containing the DRi0 (i=0-3), a third page containing the

DRi1, and so forth. These pages can be written to four bytes

at time. In this manner all four potentiometer WCRs can be

updated in a single serial write (see “Page Write Operation”),

as well as all four registers of a given page in the DR array.

The unique feature of the X9252 device is that writing or

reading to a Data Register of a given DCP automatically

updates/moves the WCR of that DCP with the content of the

DR. In this manner data can be moved from a particular DCP

register to that DCP’s WCR just by performing a 2-wire read

operation. Simultaneously, that data byte can be utilized by

the host.

Status Register Organization

The Status Register (SR) is used in read and write

operations to select the appropriate DCP register. Before

any DCP register can be accessed, the SR must be set to

the correct value. It is accessed by setting the Address Byte

to 07h (See Table 3). Do this by Writing the Slave Address

followed by a Byte Address of 07h. The SR is volatile and

defaults to 00h on power up. It is an 8-bit register containing

three control bits in the 3 LSBs as follows:

Bits DRSel1 and DRSel0 determine which Data Register of a

DCP is selected for a given operation. NVEnable is used to

select the volatile WCR if “0”, and one of the nonvolatile

DCP registers if “1”. Table 2 shows this register organization.

“Store” operations using the Up/Down interface require that

bits DRSel1 and DRSel0 are set to “0”.

ACK returned?

Issue Slave Address

Byte (Read or Write)

Byte load completed by issuing

STOP. Enter ACK Polling

Issue STOP

Issue START

NO

YES

NO

Continue normal Read or Write

command sequence

PROCEED

YES

complete. Continue command

sequence.

High Voltage

Issue STOP

FIGURE 5. ACKNOWLEDGE POLLING SEQUENCE

7

6543

2

1

0

Reserved

DRSel1

DRSel0

NVEnable

X9252

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X9252TV24I-2.7 Datasheet(PDF) 11 Page - Intersil Corporation

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