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X9252 Datasheet(PDF) 8 Page - Intersil Corporation |
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X9252 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 19 page 8 FN8167.1 September 14, 2005 Test Circuit Equivalent Circuit Principles of Operation The X9252 is an integrated circuit incorporating four resistor arrays, their associated registers and counters, and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. This section provides detail description of the following: -Resistor Array - Up/Down Interface - 2-wire Interface Resistor Array Description The X9252 is comprised of four resistor arrays. Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi inputs) (See Figure 1.) At both ends of each array and between each resistor segment is a switch connected to the wiper (RWi) pin. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select and enable one of 256 switches (see Table 1). Note that each wiper has a dedicated WCR. When all bits of a WCR are zeroes, the switch closest to the corresponding RL pin is selected. When all bits of a WCR are ones, the switch closest to the corresponding RH pin is selected. The WCR is volatile and may be written directly. There are four non-volatile Data Registers (DR) associated with each WCR. Each DR can be loaded into WCR. All DRs and WCRs can be read or written. Power Up and Down Requirements During power up, CS must be high, to avoid inadvertant “store” operations. At power up, the contents of Data Registers DR00, DR10, DR20, and DR30, are loaded into the corresponding wiper counter register. Force Current Test Point RW CH CL RW RTOTAL CW RH RL One WCR[7:0] RHi RWi RLi = FF hex 255 254 253 252 of 256 Decoder Volatile 8-bit Wiper Counter Register WCRi Four Non-Volatile Data Registers DRi0, DRi1, DRi2, and DRi3 i = 0, 1, 2, and 3 Interface Control and WCR[7:0] = 00 hex 2 1 0 Volatile Status Register (SR) (Shared by the Four DCPs) WP SCL SDA A2, A1, A0 CS U/D DS1, DS0 FIGURE 1. DETAILED BLOCK DIAGRAM OF ONE DCP X9252 |
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