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X28C010RI-20 Datasheet(PDF) 3 Page - Intersil Corporation |
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X28C010RI-20 Datasheet(HTML) 3 Page - Intersil Corporation |
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3 / 23 page  3 FN8105.0 May 11, 2005 Block Diagram Pin Descriptions Addresses (A0-A16) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers, and is used to initiate read operations. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X28C010 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28C010. Device Operation Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C010 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. X Buffers Latches and Decoder I/O Buffers and Latches Y Buffers Decoder Control Logic and Timing 1Mbit EEPROM Array I/O0-I/O7 Data Inputs/Outputs CE OE VCC VSS WE A0-A7 Latches and A8-A16 Pin Names SYMBOL DESCRIPTION A0-A16 Address Inputs I/O0-I/O7 Data Input/Output WE Write Enable CE Chip Enable OE Output Enable VCC +5V VSS Ground NC No Connect X28C010 |
Similar Part No. - X28C010RI-20 |
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Similar Description - X28C010RI-20 |
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