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X28HC64JI-70 Datasheet(PDF) 7 Page - Intersil Corporation |
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X28HC64JI-70 Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 16 page 7 FN8109.0 June 1, 2005 SOFTWARE DATA PROTECTION Figure 6. Timing Sequence—Byte or Page Write Figure 7. Write Sequence for Software Data Protection Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used, the X28HC64 will automatically dis- able further writes unless another command is issued to deactivate it. If no further commands are issued the X28HC64 will be write protected during power-down and after any subsequent power-up. Note: Once initiated, the sequence of write operations should not be interrupted. CE WE (VCC) Write Protected VCC 0V Data ADDR AAA 1555 55 0AAA A0 1555 ≤t BLC MAX Writes OK Byte or Page tWC Write Last Write Data XX to Any Write Data A0 to Address 1555 Write Data 55 to Address 0AAA Write Data AA to Address 1555 After tWC Re-Enters Data Protected State Byte to Last Address Address Optional Byte/Page Load Operation Byte/Page Load Enabled X28HC64 |
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