7

FN9189.1

July 22, 2005

UGATE (Pin 26)

Connect this pin to the upper MOSFET’s gate. This pin

provides the PWM-controlled gate drive for the upper

MOSFET. This pin is also monitored by the adaptive shoot-

through protection circuitry to determine when the upper

MOSFET has turned off. Do not insert any circuitry between

this pin and the gate of the upper MOSFET, as it may

interfere with the internal adaptive shoot-through protection

circuitry and render it ineffective.

LGATE (Pin 28)

Connect this pin to the lower MOSFET’s gate. This pin

provides the PWM-controlled gate drive for the lower

MOSFET. This pin is also monitored by the adaptive shoot-

through protection circuitry to determine when the lower

MOSFET has turned off. Do not insert any circuitry between

this pin and the gate of the lower MOSFET, as it may

interfere with the internal adaptive shoot-through protection

circuitry and render it ineffective.

FB (Pin 15) and COMP (Pin 16)

control loop. FB is the negative input to the voltage loop error

resistor divider connected to FB. With a properly selected

rail (reduced by converter losses) and the 0.8V reference.

Loop compensation is achieved by connecting an AC

network across COMP and FB.

The FB pin is also monitored for under and overvoltage

events.

PHASE (Pin 24)

Connect this pin to the upper MOSFET’s source. This pin is

used to monitor the voltage drop across the upper MOSFET

for overcurrent protection.

OCSET (Pin 22)

set the converter overcurrent (OC) trip point according to the

following equation:

An overcurrent trip cycles the soft-start function.

VDDQ (Pins 7, 8)

The VDDQ pins should be connected externally together to

Reference precision divider.

DDR_VTT (Pins 5, 6)

The DDR_VTT pins should be connect externally together.

During S0/S1 states, the DDR_VTT pins serve as the

regulator is disabled.

DDR_VTTSNS (Pin 9)

point of desired regulation.

VREF_IN (Pin 14)

is required. This capacitor and the parallel combination of

time constant for the start up ramp when transitioning from

S3/S4/S5 to S0/S1/S2.

following equation:

BOOT (Pin 25)

This pin provides ground referenced bias voltage to the

upper MOSFET driver. A bootstrap circuit is used to create a

voltage suitable to drive a logic-level N-channel MOSFET.

PWM4 (Pin 19)

This pin provides the PWM output for the GMCH core

switching regulator. Connect this pin to the PWM input of an

Intersil MOSFET driver.

FB4 (Pin 18) and COMP4 (Pin 17)

The GMCH core switching regulator employs a single

voltage control loop. FB4 is the negative input to the voltage

loop error amplifier. The GMCH core output voltage is set by

an external resistor divider connected to FB4. With a

between the power rail (reduced by converter losses) and

the 0.8V reference. Loop compensation is achieved by

connecting an AC network across COMP4 and FB4.

The FB4 pin is also monitored for undervoltage events.

FB2 (Pin 11)

this pin through a properly sized resistor divider. The voltage

at this pin is regulated to 0.8V. This pin is monitored for

undervoltage events.

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ISL6548A