9

FN9188.1

February 9, 2005

The digital soft-start for the PWM regulator is accomplished by

clamping the error amplifier reference input to a level

proportional to the internal digital soft-start voltage. As the soft-

start voltage slews up, the PWM comparator generates PHASE

pulses of increasing width that charge the output capacitor(s).

This method provides a rapid and controlled output voltage rise.

The linear regulators, with the exception of the internal

error amplifier reference is clamped to the internal digital

soft-start voltage. As the soft-start voltage ramps up, the

respective DRIVE pin voltages increase, thus enhancing the

N-MOSFETs and charging the output capacitors in a

controlled manner.

internal regulator is soft-started.

allows the termination voltage to float during the S3 sleep

enters S0 state from a sleep state, this short is released and

voltage rise on the capacitor that is tied to the VREF_IN pin.

The voltage on this capacitor is the reference for the

Description section for proper sizing of the VREF_IN

capacitor).

VIDPGD comparator is enabled. Once enabled if the

will be forced to a high impedance state.

Active to Sleep (S0 to S3 Transition)

When SLP_S3 goes LOW with SLP_S5 still HIGH, the

regulator, which is continually supplied by the 5VDUAL rail.

leakage characteristics of the memory and MCH I/O pins. It

0V. Figure 1 shows how the individual regulators are

Sleep to Active (S3 to S0 Transition)

When SLP_S3 transitions from LOW to HIGH with SLP_S5

held HIGH and after the 12V rail exceeds POR, the ISL6548

will initiate the soft-start sequence. This sequence is very

similar to the mechanical start soft-start sequencing. The

transition from S3 to S0 is represented in Figure 1 between

has exceeded the POR threshold and the ISL6548 enters a

soft-start cycle reset is ended and the individual regulators

are enabled and soft-started in the same sequence as the

mechanical cold start sequence, with the exception that the

Active to Shutdown (S0 to S5 Transition)

When the system transitions from active, S0, state to

shutdown, S4/S5, state, the ISL6548 IC disables all

regulators and forces the VIDPGD pin LOW. This transition

Fault Protection

for under and overvoltage events. All other regulators are

monitored for undervoltage events.

regulator will cause an immediate shutdown of all regulators.

This can only be cleared by toggling the SLP_S5 signal such

that the system enters the S5 sleep state and then

transitions back to the active, S0, state.

If a regulator experiences any other fault condition (an

regulator, and only that regulator, will be disabled and an

internal fault counter will be incremented by 1. If the disabled

regulator is used as the input for another regulator, then that

cascoded regulator will also experience a fault condition due

to a loss of input. The cascoded regulator will be disabled

and the fault counter incremented by 1.

At every fault occurrence, the internal fault counter is

incremented by 1 and an internal Fault Reset Counter is

cleared to zero. The Fault Reset Counter will increment once

for every clock cycle (1 clock cycle is typically 1/250kHz, or

4

µs). If the Fault Reset Counter reaches a count of 16384

before another fault occurs, then the Fault Counter is

cleared to 0. If a fault occurs prior to the Fault Reset Counter

reaching a count of 16384, then the Fault Reset Counter is

set back to zero.

The ISL6548 will immediately shut down when the Fault

Counter reaches a count of 4 when the system is restarting

from an S5 state into the active, or S0, state. The ISL6548

ISL6548