9

FN9040.2

October 4, 2005

Soft-Start Operation

When soft-start is initiated, the voltage on the SS pin of the

enabled PWM channels starts to ramp gradually, due to the

5

µA current sourced into the external capacitor. The output

voltage follows the soft-start voltage.

When the SS pin voltage reaches 0.8V, the output voltage of

the enabled PWM channel reaches the regulation point, and

the soft-start pin voltage continues to rise. At this point the

PGOOD and fault circuitry is enabled. This completes the

soft-start sequence. Any further rise of SS pin voltage does

not affect the output voltage. By varying the values of the

soft-start capacitors, it is possible to provide sequencing of the

main outputs at start-up. The soft-start time can be obtained

from the following equation:

The soft-start capacitors can be chosen to provide startup

tracking for the two PWM outputs. This can be achieved by

choosing the soft-start capacitors such that the soft-start

capacitor ration equals the respective PWM output voltage

ratio. For example, if I use PWM1 = 1.2V and PWM2 = 3.3V

1.2/3.3 = 0.364. Figure 14 shows that soft-start waveform

Output Voltage Programming

A resistive divider from the output to ground sets the output

voltage of either PWM channel. The center point of the

divider shall be connected to FBx pin. The output voltage

value is determined by the following equation.

where R1 is the top resistor of the feedback divider network

and R2 is the resistor connected from FB1 or FB2 to ground.

Out-of-Phase Operation

of-phase to reduce input ripple current. This reduces the

input capacitor ripple current requirements, reduces power

supply-induced noise, and improves EMI. This effectively

helps to lower component cost, save board space and

reduce EMI.

Dual PWMs typically operate in-phase and turn on both

upper FETs at the same time. The input capacitor must then

support the instantaneous current requirements of both

controllers simultaneously, resulting in increased ripple

voltage and current. The higher RMS ripple current lowers

the efficiency due to the power loss associated with the ESR

of the input capacitor. This typically requires more low-ESR

capacitors in parallel to minimize the input voltage ripple and

ESR-related losses, or to meet the required ripple current

rating.

With dual synchronized out-of-phase operation, the high-

The instantaneous input current peaks of both regulators no

longer overlap, resulting in reduced RMS ripple current and

input voltage ripple. This reduces the required input

capacitor ripple current rating, allowing fewer or less

expensive capacitors, and reducing the shielding

requirements for EMI. The typical operating curves show the

synchronized 180 degree out-of-phase operation.

0.8V

5

µA

-----------





=

FIGURE 13. SOFT-START OPERATION

VCC5 1V/DIV

SS1 1V/DIV

FIGURE 14. PWM1 AND PWM2 OUTPUT TRACKING DURING

STARTUP

0.8V

R1 R2

+

R2

----------------------





=

ISL6440