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MC14536BDWR2 Datasheet(PDF) 10 Page - ON Semiconductor |
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MC14536BDWR2 Datasheet(HTML) 10 Page - ON Semiconductor |
10 / 16 page MC14536B http://onsemi.com 10 FUNCTIONAL TEST SEQUENCE Inputs Outputs Comments In1 Set Reset 8–Bypass Decade Out Q1 thru Q24 All 24 stages are in Reset mode. 1 0 1 1 0 g 1 1 1 1 0 Counter is in three 8 stage sections in parallel mode. 0 1 1 1 0 First “1” to “0” transition of clock. 1 0 — — — 1 1 1 255 “1” to “0” transitions are clocked in the counter. 0 1 1 1 1 The 255 “1” to “0” transition. 0 0 0 0 1 Counter converted back to 24 stages in series mode. Set and Reset must be connected together and simultaneously go from “1” to “0”. 1 0 0 0 1 In1 Switches to a “1”. 0 0 0 0 0 Counter Ripples from an all “1” state to an all “0” state. |
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