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EP7312-IV-90 Datasheet(PDF) 11 Page - Cirrus Logic |
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EP7312-IV-90 Datasheet(HTML) 11 Page - Cirrus Logic |
11 / 64 page DS508PP5 ©Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) 11 EP7312 High-Performance, Low-Power System on Chip Pin Multiplexing Table 18 shows the pin multiplexing of the DAI, SSI2 and the CODEC. The selection between SSI2 and the CODEC is controlled by the state of the SERSEL bit in SYSCON2. Thechoicebetween theSSI2, CODEC, and the DAIis controlled by the DAISEL bit in SYSCON3 (see the EP7312 User’s Manual for more information). Table 19 shows the pins that have been multiplexed in the EP7312. Table 18. DAI/SSI2/CODEC Pin Multiplexing Pin Mnemonic I/O DAI SSI2 CODEC SSICLK I/O SCLK SSICLK PCMCLK SSITXDA O SDOUT SSITXDA PCMOUT SSIRXDA I SDIN SSIRXDA PCMIN SSITXFR I/O LRCK SSITXFR PCMSYNC SSIRXFR I MCLKIN SSIRXFR p/u BUZ O MCLKOUT Table 19. Pin Multiplexing Signal Block Signal Block nMOE Static Memory nSDCAS SDRAM nMWE Static Memory nSDWE SDRAM WRITE Static Memory nSDRAS SDRAM A[27:15] Static Memory DRA[0:12] SDRAM A[14:13] Static Memory DRA[13:14] SDRAM PD[7:6] GPIO SDQM[1:0] SDRAM RUN System Configuration CLKEN System Configuration nMEDCHG Interrupt Controller nBROM Boot ROM select PD[0] GPIO LEDFLSH LED Flasher PE[1:0] GPIO BOOTSEL[1:0] System Configuration PE[2] GPIO CLKSEL System Configuration |
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