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C8051F123 Datasheet(PDF) 7 Page - Silicon Laboratories |
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C8051F123 Datasheet(HTML) 7 Page - Silicon Laboratories |
7 / 356 page Rev. 1.3 7 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 20.1.4.Slave Select (NSS) ................................................................................ 278 20.2.SPI0 Master Mode Operation ......................................................................... 279 20.3.SPI0 Slave Mode Operation ........................................................................... 281 20.4.SPI0 Interrupt Sources ................................................................................... 281 20.5.Serial Clock Timing......................................................................................... 282 20.6.SPI Special Function Registers ...................................................................... 284 21. UART0.................................................................................................................... 291 21.1.UART0 Operational Modes ............................................................................ 292 21.1.1.Mode 0: Synchronous Mode .................................................................. 292 21.1.2.Mode 1: 8-Bit UART, Variable Baud Rate.............................................. 293 21.1.3.Mode 2: 9-Bit UART, Fixed Baud Rate .................................................. 295 21.1.4.Mode 3: 9-Bit UART, Variable Baud Rate.............................................. 296 21.2.Multiprocessor Communications .................................................................... 297 21.2.1.Configuration of a Masked Address ....................................................... 297 21.2.2.Broadcast Addressing ............................................................................ 297 21.3.Frame and Transmission Error Detection....................................................... 298 22. UART1.................................................................................................................... 303 22.1.Enhanced Baud Rate Generation................................................................... 304 22.2.Operational Modes ......................................................................................... 305 22.2.1.8-Bit UART ............................................................................................. 305 22.2.2.9-Bit UART ............................................................................................. 306 22.3.Multiprocessor Communications .................................................................... 307 23. Timers.................................................................................................................... 313 23.1.Timer 0 and Timer 1 ....................................................................................... 313 23.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 313 23.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 314 23.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 315 23.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 316 23.2.Timer 2, Timer 3, and Timer 4 ........................................................................ 322 23.2.1.Configuring Timer 2, 3, and 4 to Count Down........................................ 322 23.2.2.Capture Mode ........................................................................................ 323 23.2.3.Auto-Reload Mode ................................................................................. 324 23.2.4.Toggle Output Mode (Timer 2 and Timer 4 Only) .................................. 324 24. Programmable Counter Array ............................................................................. 331 24.1.PCA Counter/Timer ........................................................................................ 332 24.2.Capture/Compare Modules ............................................................................ 333 24.2.1.Edge-triggered Capture Mode................................................................ 334 24.2.2.Software Timer (Compare) Mode........................................................... 335 24.2.3.High Speed Output Mode....................................................................... 336 24.2.4.Frequency Output Mode ........................................................................ 337 24.2.5.8-Bit Pulse Width Modulator Mode......................................................... 338 24.2.6.16-Bit Pulse Width Modulator Mode....................................................... 339 24.3.Register Descriptions for PCA0...................................................................... 340 25. JTAG (IEEE 1149.1) .............................................................................................. 345 25.1.Boundary Scan ............................................................................................... 346 |
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