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ADSP-21991 Datasheet(PDF) 3 Page - Analog Devices |
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ADSP-21991 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 44 page  –3– REV. 0 ADSP-21991 The flexible architecture and comprehensive instruction set of the ADSP-21991 support multiple operations in parallel. For example, in one processor cycle, the ADSP-21991 can: • Generate an address for the next instruction fetch • Fetch the next instruction • Perform one or two data moves • Update one or two data address pointers • Perform a computational operation These operations take place while the processor continues to: • Receive and transmit data through the serial port • Receive or transmit data over the SPI port • Access external memory through the external memory interface • Decrement the timers • Operate the embedded control peripherals (ADC, PWM, EIU, etc.) DSP Core Architecture • 6.25 ns instruction cycle time (internal), for up to 160 MIPS sustained performance (6.67 ns instruction cycle time for 150 MIPS sustained performance) • ADSP-218x family code compatible with the same easy to use algebraic syntax • Single cycle instruction execution • Up to 1M words of addressable memory space with twenty four bits of addressing width • Dual purpose program memory for both instruction and data storage • Fully transparent instruction cache allows dual operand fetches in every instruction cycle • Unified memory space permits flexible address genera- tion, using two independent DAG units • Independent ALU, multiplier/accumulator, and barrel shifter computational units with dual 40-bit accumulators • Single cycle context switch between two sets of computa- tional and DAG registers • Parallel execution of computation and memory instructions • Pipelined architecture supports efficient code execution at speeds up to 160 MIPS • Register file computations with all nonconditional, non- parallel computational instructions • Powerful program sequencer provides zero overhead looping and conditional instruction execution • Architectural enhancements for compiled C code efficiency • Architecture enhancements beyond ADSP-218x family are supported with instruction set extensions for added registers, ports, and peripherals. The clock generator module of the ADSP-21991 includes clock control logic that allows the user to select and change the main clock frequency. The module generates two output clocks: the DSP core clock, CCLK; and the peripheral clock, HCLK. CCLK can sustain clock values of up to 160 MHz, while HCLK can be equal to CCLK or CCLK/2 for values up to a maximum 80 MHz peripheral clock at the 160 MHz CCLK rate. The ADSP-21991 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every single word instruction can be executed in a single processor cycle. The ADSP-21991 assembly language uses an algebraic syntax for ease of coding and readability. A compre- hensive set of development tools supports program development. The block diagram Figure 1 shows the architecture of the embedded ADSP-219x core. It contains three independent com- putational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data from the register file and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single cycle multiply, multiply/add, and multi- ply/subtract operations. The MAC has two 40-bit accumulators, which help with overflow. The shifter performs logical and arith- metic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control, including multiword and block floating point representations. Register usage rules influence placement of input and results within the computational units. For most operations, the data registers of the computational units act as a data register file, permitting any input or result register to provide input to any unit for a computation. For feedback operations, the computational units let the output (result) of any unit be input to any unit on the next cycle. For conditional or multifunction instructions, there are restrictions on which data registers may provide inputs or receive results from each computational unit. For more infor- mation, see the ADSP-219x DSP Instruction Set Reference. A powerful program sequencer controls the flow of instruction execution. The sequencer supports conditional jumps, subrou- tine calls, and low interrupt overhead. With internal loop counters and loop stacks, the ADSP-21991 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four 16-bit address pointers. Whenever the pointer is used to access data (indirect addressing), it is pre- or post-modified by the value of one of four possible modify registers. A length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers. Page registers in the DAGs allow circular addressing within 64K word bound- aries of each of the 256 memory pages, but these buffers may not cross page boundaries. Secondary registers duplicate all the primary registers in the DAGs; switching between primary and secondary registers provides a fast context switch. |
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