M41T81SM6F datasheet(6/29 Pages) STMICROELECTRONICS

Part #	M41T81SM6F

Description	Serial Access Real-Time Clock with Alarms

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M41T81S

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OPERATION

The M41T81S clock operates as a slave device on

the serial bus. Access is obtained by implementing

a start condition followed by the correct slave ad-

dress (D0h). The 20 bytes contained in the device

can then be accessed sequentially in the following

order:

1.

Tenths/Hundredths of a Second Register

2.

Seconds Register

3.

Minutes Register

4.

Century/Hours Register

5.

Day Register

6.

Date Register

7.

Month Register

8.

Year Register

9.

Calibration Register

10. Watchdog Register

11 - 15. Alarm Registers

16. Flags Register

17 - 19. Reserved

20. Square Wave Register

The M41T81S clock continually monitors VCC for

an out-of-tolerance condition. Should VCC fall be-

low VPFD, the device terminates an access in

progress and resets the device address counter.

Inputs to the device will not be recognized at this

time to prevent erroneous data from being written

to the device from a an out-of-tolerance system.

Once VCC falls below the switchover voltage

(VSO), the device automatically switches over to

the battery and powers down into an ultra-low cur-

rent mode of operation to preserve battery life. If

VBAT is less than VPFD, the device power is

switched from VCC to VBAT when VCC drops below

VBAT. If VBAT is greater than VPFD, the device

power is switched from VCC to VBAT when VCC

drops below VPFD. Upon power-up, the device

switches from battery to VCC at VSO. When VCC

rises above VPFD, it will recognize the inputs.

For more information on Battery Storage Life refer

to Application Note AN1012.

2-Wire Bus Characteristics

The bus is intended for communication between

different ICs. It consists of two lines: a bi-direction-

al data signal (SDA) and a clock signal (SCL).

Both the SDA and SCL lines must be connected to

a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

–

Data transfer may be initiated only when the

bus is not busy.

–

During data transfer, the data line must remain

stable whenever the clock line is High.

–

Changes in the data line, while the clock line is

High, will be interpreted as control signals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer. A change in the state of the

data line, from high to Low, while the clock is High,

defines the START condition.

Stop data transfer. A change in the state of the

data line, from Low to High, while the clock is High,

defines the STOP condition.

Data Valid. The state of the data line represents

valid data when after a start condition, the data line

is stable for the duration of the high period of the

clock signal. The data on the line may be changed

during the Low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated with a start condition

and terminated with a stop condition. The number

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte-wide and each receiver acknowl-

edges with a ninth bit.

By definition a device that gives out a message is

called “transmitter,” the receiving device that gets

the message is called “receiver.” The device that

controls the message is called “master.” The de-

vices that are controlled by the master are called

“slaves.”

Acknowledge. Each byte of eight bits is followed

by one Acknowledge Bit. This Acknowledge Bit is

a low level put on the bus by the receiver whereas

the master generates an extra acknowledge relat-

ed clock pulse. A slave receiver which is ad-

dressed is obliged to generate an acknowledge

after the reception of each byte that has been

clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times must

be taken into account. A master receiver must sig-

nal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that

has been clocked out of the slave. In this case the

transmitter must leave the data line High to enable

the master to generate the STOP condition.

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