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IS42LS16800A Datasheet(PDF) 1 Page - Integrated Circuit Solution Inc |
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IS42LS16800A Datasheet(HTML) 1 Page - Integrated Circuit Solution Inc |
1 / 66 page Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 ADVANCEDINFORMATION,Rev. 00A 08/01/02 Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. IS42S81600A, IS42LS81600A IS42S16800A, IS42LS16800A IS42S32400A, IS42LS32400A ISSI® FEATURES • Clock frequency: 133 100, MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply VDD VDDQ IS42LS81600A 2.5V 1.8V (2.5V tolerant) IS42LS16800A 2.5V 1.8V (2.5V tolerant) IS42LS32400A 2.5V 1.8V (2.5V tolerant) IS42S81600A 3.3V 3.3V IS42S16800A 3.3V 3.3V IS42S32400A 3.3V 3.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Extended Mode Register • Programmable Power Reduction Feature by partial array activation during Self-Refresh • Auto Refresh (CBR) • Temp. Compensated Self Refresh. • Self Refresh with programmable refresh periods • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Industrial Temperature Availability OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDARM is organized as follows. 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM ADVANCED INFORMATION AUGUST 2002 KEY TIMING PARAMETERS Parameter -7 -10 Unit Clk Cycle Time CAS Latency = 3 7 10 ns CAS Latency = 2 10 10 ns Clk Frequency CAS Latency = 3 133 100 Mhz CAS Latency = 2 100 100 Mhz Access Time from Clock CAS Latency = 3 5.4 7 ns CAS Latency = 2 6 9 ns Row to Column Delay Time (tRCD) 1518ns Row Precharge Tim (tRP) 1518ns IS42LS81600A IS42LS16800A IS42LS32400A IS42S81600A IS42S16800A IS42S32400A 4M x8x4 Banks 2M x16x4 Banks 2M x16x4 Banks 54pin TSOPII 54ball FBGA 90ball FBGA 54 pin TSOPII 86pin TSOPII |
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