1
Selection Guide
27C128-45 27C128-55 27C128-70 27C128-90 27C128-120 27C128-150 27C128-200
MaximumAccessTime(ns)
45
55
70
90
120
150
200
Maximum
Operating
Com'l
45
45
45
45
45
45
45
Operating
Current (mA)[2]
Mil
55
55
55
55
55
55
55
Standby Current
(A)
Com'l
15
15
15
15
15
15
15
Standby Current
(mA)
Mil
20
20
20
20
20
20
20
Chip Select Time (ns)
45
55
70
90
120
150
200
Output Enable Time (ns)
15
20
25
30
30
40
40
Notes:
1. For PLCC only: Pins 1 and 17 are common and tied to the die attach
pad. They must therefore be DU (don't use) for the PLCC package.
2. Add 2 mA/MHz for AC power component.
CY27C128
128K (16K x 8Bit) CMOS EPROM
Features
D
Wide speed range
45 ns to 200 ns (commercial and
military)
D
Low power
248 mW (commercial)
303 mW (military)
D
Low standby power
Less than 83 mW when deselected
D
±10% Power supply tolerance
Functional Description
The CY27C128 is a highperformance
16,384word by 8bit CMOS EPROM.
When disabled (CE HIGH), the
CY27C128 automatically powers down
into a lowpower standby mode. The
CY27C128 is packaged in the industry
standard 600mil DIP and LCC packages.
The CY27C128 is also available in a Cer
DIP package equipped with an erasure
window to provide for reprogrammability.
When exposed to UV light, the EPROM
is erased and can be reprogrammed. The
memory cells utilize proven EPROM
floating gate technology and bytewide in
telligent programming algorithms.
The CY27C128 offers the advantage of
lower power and superior performance and
programming yield. The EPROM cell re
quires only 12.5V for the super voltage,
and low current requirements allow for
gang programming. The EPROM cells al
low each memory location to be tested
100% because each location is written
into, erased, and repeatedly exercised
prior to encapsulation. Each EPROM is
also tested for AC performance to guar
antee that after customer programming,
the product will meet both DC and AC
specification limits.
Reading the CY27C128 is accomplished
by placing active LOW signals on OE and
CE. The contents of the memory location
addressed by the address lines (A0 - A13)
will become available on the output lines
(O0 - O7).
Logic Block Diagram
Pin Configurations
C1281
A12
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
POWERDOWN
O7
O6
O5
O4
O3
O2
O1
O0
CE
128 x 1024
PROGRAMABLE
ARRAY
8 x 1 OF 128
MULTIPLEXER
A10
A13
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
12
31
4
5
6
7
8
9
10
32 1
30
13
14 15 16 17
26
25
24
23
22
21
11
1819 20
27
28
29
32
15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A13
A8
A9
O7
O6
O4
O5
O3
C1282
C1283
A9
A11
O7
O6
A8
VPP
PGM
27C128
A11
OE
A10
CE
NC
A5
A4
A3
A2
A6
A1
O0
A0
NC
OE
A10
CE
DIP/Flatpack
27C128
ROW
LCC/PLCC [1]
OE
ADDRESS
COLUMN
ADDRESS
ADDRESS
DECODER
Cypress Semiconductor Corporation
D
3901 North First Street
D San Jose D
CA 95134
D 408-943-2600
February 1994
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